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ip_templates/rv_core_ibex/rtl
top_darjeeling/ip_autogen/rv_core_ibex/rtl
top_earlgrey/ip_autogen/rv_core_ibex/rtl
top_englishbreakfast/ip_autogen/rv_core_ibex/rtl Expand file tree Collapse file tree 4 files changed +0
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lines changed Original file line number Diff line number Diff line change @@ -1055,14 +1055,6 @@ module ${module_instance_name}
10551055
10561056 // Alert assertions for reg_we onehot check
10571057 `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg_cfg, alert_tx_o[2])
1058- `ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT(RvCoreRegWeOnehotCheck_A,
1059- u_core.gen_regfile_ff.register_file_i.gen_wren_check.u_prim_onehot_check, alert_tx_o[2])
1060- `ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT(RvCoreRegWeOnehotCheckRAddrA_A,
1061- u_core.gen_regfile_ff.register_file_i.gen_rdata_mux_check.u_prim_onehot_check_raddr_a,
1062- alert_tx_o[2])
1063- `ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT(RvCoreRegWeOnehotCheckRAddrB_A,
1064- u_core.gen_regfile_ff.register_file_i.gen_rdata_mux_check.u_prim_onehot_check_raddr_b,
1065- alert_tx_o[2])
10661058
10671059`ifdef INC_ASSERT
10681060 if (ICache && ICacheScramble) begin : gen_icache_scramble_asserts
Original file line number Diff line number Diff line change @@ -1027,14 +1027,6 @@ module rv_core_ibex
10271027
10281028 // Alert assertions for reg_we onehot check
10291029 `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT (RegWeOnehotCheck_A, u_reg_cfg, alert_tx_o[2 ])
1030- `ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT (RvCoreRegWeOnehotCheck_A,
1031- u_core.gen_regfile_ff.register_file_i.gen_wren_check.u_prim_onehot_check, alert_tx_o[2 ])
1032- `ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT (RvCoreRegWeOnehotCheckRAddrA_A,
1033- u_core.gen_regfile_ff.register_file_i.gen_rdata_mux_check.u_prim_onehot_check_raddr_a,
1034- alert_tx_o[2 ])
1035- `ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT (RvCoreRegWeOnehotCheckRAddrB_A,
1036- u_core.gen_regfile_ff.register_file_i.gen_rdata_mux_check.u_prim_onehot_check_raddr_b,
1037- alert_tx_o[2 ])
10381030
10391031`ifdef INC_ASSERT
10401032 if (ICache && ICacheScramble) begin : gen_icache_scramble_asserts
Original file line number Diff line number Diff line change @@ -1027,14 +1027,6 @@ module rv_core_ibex
10271027
10281028 // Alert assertions for reg_we onehot check
10291029 `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT (RegWeOnehotCheck_A, u_reg_cfg, alert_tx_o[2 ])
1030- `ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT (RvCoreRegWeOnehotCheck_A,
1031- u_core.gen_regfile_ff.register_file_i.gen_wren_check.u_prim_onehot_check, alert_tx_o[2 ])
1032- `ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT (RvCoreRegWeOnehotCheckRAddrA_A,
1033- u_core.gen_regfile_ff.register_file_i.gen_rdata_mux_check.u_prim_onehot_check_raddr_a,
1034- alert_tx_o[2 ])
1035- `ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT (RvCoreRegWeOnehotCheckRAddrB_A,
1036- u_core.gen_regfile_ff.register_file_i.gen_rdata_mux_check.u_prim_onehot_check_raddr_b,
1037- alert_tx_o[2 ])
10381030
10391031`ifdef INC_ASSERT
10401032 if (ICache && ICacheScramble) begin : gen_icache_scramble_asserts
Original file line number Diff line number Diff line change @@ -1027,14 +1027,6 @@ module rv_core_ibex
10271027
10281028 // Alert assertions for reg_we onehot check
10291029 `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT (RegWeOnehotCheck_A, u_reg_cfg, alert_tx_o[2 ])
1030- `ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT (RvCoreRegWeOnehotCheck_A,
1031- u_core.gen_regfile_ff.register_file_i.gen_wren_check.u_prim_onehot_check, alert_tx_o[2 ])
1032- `ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT (RvCoreRegWeOnehotCheckRAddrA_A,
1033- u_core.gen_regfile_ff.register_file_i.gen_rdata_mux_check.u_prim_onehot_check_raddr_a,
1034- alert_tx_o[2 ])
1035- `ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT (RvCoreRegWeOnehotCheckRAddrB_A,
1036- u_core.gen_regfile_ff.register_file_i.gen_rdata_mux_check.u_prim_onehot_check_raddr_b,
1037- alert_tx_o[2 ])
10381030
10391031`ifdef INC_ASSERT
10401032 if (ICache && ICacheScramble) begin : gen_icache_scramble_asserts
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