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[rv_core_ibex,rtl] Use a LockstepDelay of 1 cycle
Switch from a 2 cycle lockstep delay to 1 cycle to save area. Signed-off-by: Pascal Nasahl <[email protected]>
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-8
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8 files changed

+32
-8
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‎hw/ip_templates/rv_core_ibex/lint/rv_core_ibex.waiver.tpl‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -133,6 +133,8 @@ waive -rules RESET_USE -location {ibex_lockstep.sv} -regexp {'enable_
133133
waive -rules {CLOCK_USE RESET_USE} -location {ibex_register_file_ff.sv} ${"\\"}
134134
-regexp {'(clk_i|rst_ni)' is connected to '(prim_onehot_mux)' port} ${"\\"}
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-comment {The module is fully combinatorial, clk/rst are only used for assertions.}
136+
waive -rules CONST_FF -location {ibex_lockstep.sv} -regexp {Flip-flop 'enable_cmp_d' is driven by constant 4'b0101} ${"\\"}
137+
-comment "The only purpose of the flop is to enable the lockstep comparison after reset"
136138

137139
# Highlighting my main concerns here, documenting areas to review in next dive
138140
#

‎hw/ip_templates/rv_core_ibex/rtl/rv_core_ibex.sv.tpl‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,7 @@ module ${module_instance_name}
4040
parameter bit DbgTriggerEn = 1'b1,
4141
parameter int unsigned DbgHwBreakNum = 4,
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parameter bit SecureIbex = 1'b1,
43+
parameter int unsigned LockstepOffset = 1,
4344
parameter ibex_pkg::lfsr_seed_t RndCnstLfsrSeed = ibex_pkg::RndCnstLfsrSeedDefault,
4445
parameter ibex_pkg::lfsr_perm_t RndCnstLfsrPerm = ibex_pkg::RndCnstLfsrPermDefault,
4546
parameter int unsigned DmBaseAddr = 32'h1A110000,
@@ -443,6 +444,7 @@ module ${module_instance_name}
443444
// SEC_CM: EXCEPTION.CTRL_FLOW.GLOBAL_ESC, EXCEPTION.CTRL_FLOW.LOCAL_ESC
444445
// SEC_CM: DATA_REG_SW.INTEGRITY, DATA_REG_SW.GLITCH_DETECT
445446
.SecureIbex ( SecureIbex ),
447+
.LockstepOffset ( LockstepOffset ),
446448
.RndCnstLfsrSeed ( RndCnstLfsrSeed ),
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.RndCnstLfsrPerm ( RndCnstLfsrPerm ),
448450
.RndCnstIbexKey ( RndCnstIbexKeyDefault ),
@@ -1121,8 +1123,10 @@ module ${module_instance_name}
11211123
lsu_store_resp_intg_err)
11221124
`ASSERT_IBEX_CORE_ERROR_TRIGGER_ALERT(IbexInstrIntgErrCheck_A, alert_tx_o[2], u_ibex_core,
11231125
instr_intg_err)
1124-
`ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(IbexLockstepResetCountAlertCheck_A,
1125-
u_core.gen_lockstep.u_ibex_lockstep.u_rst_shadow_cnt, alert_tx_o[2])
1126+
if (LockstepOffset > 1) begin: gen_lockstep_rst_cnt_assert
1127+
`ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(IbexLockstepResetCountAlertCheck_A,
1128+
u_core.gen_lockstep.u_ibex_lockstep.gen_reset_counter.u_rst_shadow_cnt, alert_tx_o[2])
1129+
end
11261130
`ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CoredTlLcGateFsm_A,
11271131
u_tlul_lc_gate_cored.u_state_regs, alert_tx_o[2])
11281132

‎hw/top_darjeeling/ip_autogen/rv_core_ibex/lint/rv_core_ibex.waiver‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -133,6 +133,8 @@ waive -rules RESET_USE -location {ibex_lockstep.sv} -regexp {'enable_
133133
waive -rules {CLOCK_USE RESET_USE} -location {ibex_register_file_ff.sv} \
134134
-regexp {'(clk_i|rst_ni)' is connected to '(prim_onehot_mux)' port} \
135135
-comment {The module is fully combinatorial, clk/rst are only used for assertions.}
136+
waive -rules CONST_FF -location {ibex_lockstep.sv} -regexp {Flip-flop 'enable_cmp_d' is driven by constant 4'b0101} \
137+
-comment "The only purpose of the flop is to enable the lockstep comparison after reset"
136138

137139
# Highlighting my main concerns here, documenting areas to review in next dive
138140
#

‎hw/top_darjeeling/ip_autogen/rv_core_ibex/rtl/rv_core_ibex.sv‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,7 @@ module rv_core_ibex
4040
parameter bit DbgTriggerEn = 1'b1,
4141
parameter int unsigned DbgHwBreakNum = 4,
4242
parameter bit SecureIbex = 1'b1,
43+
parameter int unsigned LockstepOffset = 1,
4344
parameter ibex_pkg::lfsr_seed_t RndCnstLfsrSeed = ibex_pkg::RndCnstLfsrSeedDefault,
4445
parameter ibex_pkg::lfsr_perm_t RndCnstLfsrPerm = ibex_pkg::RndCnstLfsrPermDefault,
4546
parameter int unsigned DmBaseAddr = 32'h1A110000,
@@ -430,6 +431,7 @@ module rv_core_ibex
430431
// SEC_CM: EXCEPTION.CTRL_FLOW.GLOBAL_ESC, EXCEPTION.CTRL_FLOW.LOCAL_ESC
431432
// SEC_CM: DATA_REG_SW.INTEGRITY, DATA_REG_SW.GLITCH_DETECT
432433
.SecureIbex ( SecureIbex ),
434+
.LockstepOffset ( LockstepOffset ),
433435
.RndCnstLfsrSeed ( RndCnstLfsrSeed ),
434436
.RndCnstLfsrPerm ( RndCnstLfsrPerm ),
435437
.RndCnstIbexKey ( RndCnstIbexKeyDefault ),
@@ -1093,8 +1095,10 @@ module rv_core_ibex
10931095
lsu_store_resp_intg_err)
10941096
`ASSERT_IBEX_CORE_ERROR_TRIGGER_ALERT(IbexInstrIntgErrCheck_A, alert_tx_o[2], u_ibex_core,
10951097
instr_intg_err)
1096-
`ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(IbexLockstepResetCountAlertCheck_A,
1097-
u_core.gen_lockstep.u_ibex_lockstep.u_rst_shadow_cnt, alert_tx_o[2])
1098+
if (LockstepOffset > 1) begin: gen_lockstep_rst_cnt_assert
1099+
`ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(IbexLockstepResetCountAlertCheck_A,
1100+
u_core.gen_lockstep.u_ibex_lockstep.gen_reset_counter.u_rst_shadow_cnt, alert_tx_o[2])
1101+
end
10981102
`ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CoredTlLcGateFsm_A,
10991103
u_tlul_lc_gate_cored.u_state_regs, alert_tx_o[2])
11001104

‎hw/top_earlgrey/ip_autogen/rv_core_ibex/lint/rv_core_ibex.waiver‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -133,6 +133,8 @@ waive -rules RESET_USE -location {ibex_lockstep.sv} -regexp {'enable_
133133
waive -rules {CLOCK_USE RESET_USE} -location {ibex_register_file_ff.sv} \
134134
-regexp {'(clk_i|rst_ni)' is connected to '(prim_onehot_mux)' port} \
135135
-comment {The module is fully combinatorial, clk/rst are only used for assertions.}
136+
waive -rules CONST_FF -location {ibex_lockstep.sv} -regexp {Flip-flop 'enable_cmp_d' is driven by constant 4'b0101} \
137+
-comment "The only purpose of the flop is to enable the lockstep comparison after reset"
136138

137139
# Highlighting my main concerns here, documenting areas to review in next dive
138140
#

‎hw/top_earlgrey/ip_autogen/rv_core_ibex/rtl/rv_core_ibex.sv‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,7 @@ module rv_core_ibex
4040
parameter bit DbgTriggerEn = 1'b1,
4141
parameter int unsigned DbgHwBreakNum = 4,
4242
parameter bit SecureIbex = 1'b1,
43+
parameter int unsigned LockstepOffset = 1,
4344
parameter ibex_pkg::lfsr_seed_t RndCnstLfsrSeed = ibex_pkg::RndCnstLfsrSeedDefault,
4445
parameter ibex_pkg::lfsr_perm_t RndCnstLfsrPerm = ibex_pkg::RndCnstLfsrPermDefault,
4546
parameter int unsigned DmBaseAddr = 32'h1A110000,
@@ -430,6 +431,7 @@ module rv_core_ibex
430431
// SEC_CM: EXCEPTION.CTRL_FLOW.GLOBAL_ESC, EXCEPTION.CTRL_FLOW.LOCAL_ESC
431432
// SEC_CM: DATA_REG_SW.INTEGRITY, DATA_REG_SW.GLITCH_DETECT
432433
.SecureIbex ( SecureIbex ),
434+
.LockstepOffset ( LockstepOffset ),
433435
.RndCnstLfsrSeed ( RndCnstLfsrSeed ),
434436
.RndCnstLfsrPerm ( RndCnstLfsrPerm ),
435437
.RndCnstIbexKey ( RndCnstIbexKeyDefault ),
@@ -1093,8 +1095,10 @@ module rv_core_ibex
10931095
lsu_store_resp_intg_err)
10941096
`ASSERT_IBEX_CORE_ERROR_TRIGGER_ALERT(IbexInstrIntgErrCheck_A, alert_tx_o[2], u_ibex_core,
10951097
instr_intg_err)
1096-
`ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(IbexLockstepResetCountAlertCheck_A,
1097-
u_core.gen_lockstep.u_ibex_lockstep.u_rst_shadow_cnt, alert_tx_o[2])
1098+
if (LockstepOffset > 1) begin: gen_lockstep_rst_cnt_assert
1099+
`ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(IbexLockstepResetCountAlertCheck_A,
1100+
u_core.gen_lockstep.u_ibex_lockstep.gen_reset_counter.u_rst_shadow_cnt, alert_tx_o[2])
1101+
end
10981102
`ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CoredTlLcGateFsm_A,
10991103
u_tlul_lc_gate_cored.u_state_regs, alert_tx_o[2])
11001104

‎hw/top_englishbreakfast/ip_autogen/rv_core_ibex/lint/rv_core_ibex.waiver‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -133,6 +133,8 @@ waive -rules RESET_USE -location {ibex_lockstep.sv} -regexp {'enable_
133133
waive -rules {CLOCK_USE RESET_USE} -location {ibex_register_file_ff.sv} \
134134
-regexp {'(clk_i|rst_ni)' is connected to '(prim_onehot_mux)' port} \
135135
-comment {The module is fully combinatorial, clk/rst are only used for assertions.}
136+
waive -rules CONST_FF -location {ibex_lockstep.sv} -regexp {Flip-flop 'enable_cmp_d' is driven by constant 4'b0101} \
137+
-comment "The only purpose of the flop is to enable the lockstep comparison after reset"
136138

137139
# Highlighting my main concerns here, documenting areas to review in next dive
138140
#

‎hw/top_englishbreakfast/ip_autogen/rv_core_ibex/rtl/rv_core_ibex.sv‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,7 @@ module rv_core_ibex
4040
parameter bit DbgTriggerEn = 1'b1,
4141
parameter int unsigned DbgHwBreakNum = 4,
4242
parameter bit SecureIbex = 1'b1,
43+
parameter int unsigned LockstepOffset = 1,
4344
parameter ibex_pkg::lfsr_seed_t RndCnstLfsrSeed = ibex_pkg::RndCnstLfsrSeedDefault,
4445
parameter ibex_pkg::lfsr_perm_t RndCnstLfsrPerm = ibex_pkg::RndCnstLfsrPermDefault,
4546
parameter int unsigned DmBaseAddr = 32'h1A110000,
@@ -430,6 +431,7 @@ module rv_core_ibex
430431
// SEC_CM: EXCEPTION.CTRL_FLOW.GLOBAL_ESC, EXCEPTION.CTRL_FLOW.LOCAL_ESC
431432
// SEC_CM: DATA_REG_SW.INTEGRITY, DATA_REG_SW.GLITCH_DETECT
432433
.SecureIbex ( SecureIbex ),
434+
.LockstepOffset ( LockstepOffset ),
433435
.RndCnstLfsrSeed ( RndCnstLfsrSeed ),
434436
.RndCnstLfsrPerm ( RndCnstLfsrPerm ),
435437
.RndCnstIbexKey ( RndCnstIbexKeyDefault ),
@@ -1093,8 +1095,10 @@ module rv_core_ibex
10931095
lsu_store_resp_intg_err)
10941096
`ASSERT_IBEX_CORE_ERROR_TRIGGER_ALERT(IbexInstrIntgErrCheck_A, alert_tx_o[2], u_ibex_core,
10951097
instr_intg_err)
1096-
`ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(IbexLockstepResetCountAlertCheck_A,
1097-
u_core.gen_lockstep.u_ibex_lockstep.u_rst_shadow_cnt, alert_tx_o[2])
1098+
if (LockstepOffset > 1) begin: gen_lockstep_rst_cnt_assert
1099+
`ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(IbexLockstepResetCountAlertCheck_A,
1100+
u_core.gen_lockstep.u_ibex_lockstep.gen_reset_counter.u_rst_shadow_cnt, alert_tx_o[2])
1101+
end
10981102
`ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CoredTlLcGateFsm_A,
10991103
u_tlul_lc_gate_cored.u_state_regs, alert_tx_o[2])
11001104

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