[otbn, sca] Don't flatten the netlist when shortening signal names

When shortening signal names the shorten_alma_identifiers.py script used to
flatten the design before shortening the identifiers. This commit changes
this. Now the signal names are shortened without an initial flattening
step. This is done by adding a --reserve flag that decides how long the
unflattened signal names can get (how much should be left in reserve).

Signed-off-by: Hakim Filali <hfilali@lowrisc.org>

Author: h-filali

hw/ip/otbn/pre_sca/alma/shorten_alma_identifiers.py

@@ -30,26 +30,26 @@ def _cpp_len(identifier: str) -> int:
     return n
 
 
-def build_id_map(text: str) -> dict:
+def build_id_map(text: str, *, limit: int = VERILATOR_LIMIT) -> dict:
     """Return a mapping of long identifier -> shortened identifier (no backslashes)."""
     escaped_re = re.compile(r'\\([^ \t\n;,)(]+)')
     all_ids = set(escaped_re.findall(text))
-    long_ids = sorted(i for i in all_ids if _cpp_len(i) >= VERILATOR_LIMIT)
+    long_ids = sorted(i for i in all_ids if _cpp_len(i) >= limit)
 
     if not long_ids:
         return {}
 
     # Pre-populate 'used' with every short identifier already in the file so
     # that trimmed names never collide with pre-existing signals.
-    used = {i for i in all_ids if _cpp_len(i) < VERILATOR_LIMIT}
+    used = {i for i in all_ids if _cpp_len(i) < limit}
 
     id_map = {}
     for ident in long_ids:
         segments = ident.split('.')
         chosen = None
         for start in range(len(segments)):
             base = '.'.join(segments[start:])
-            if _cpp_len(base) >= VERILATOR_LIMIT:
+            if _cpp_len(base) >= limit:
                 continue
             if base not in used:
                 chosen = base
@@ -58,7 +58,7 @@ def build_id_map(text: str) -> dict:
             n = 2
             while True:
                 candidate = f'{base}_{n}'
-                if _cpp_len(candidate) >= VERILATOR_LIMIT:
+                if _cpp_len(candidate) >= limit:
                     break  # suffix too long at this trim depth — drop more segments
                 if candidate not in used:
                     chosen = candidate
@@ -67,14 +67,14 @@ def build_id_map(text: str) -> dict:
             if chosen is not None:
                 break
         if chosen is None:
-            base = segments[-1][:VERILATOR_LIMIT - 1]
+            base = segments[-1][:limit - 1]
             if base not in used:
                 chosen = base
             else:
                 n = 2
                 while True:
                     suffix = f'_{n}'
-                    chosen = base[:VERILATOR_LIMIT - 1 - len(suffix)] + suffix
+                    chosen = base[:limit - 1 - len(suffix)] + suffix
                     if chosen not in used:
                         break
                     n += 1
@@ -84,15 +84,15 @@ def build_id_map(text: str) -> dict:
     return id_map
 
 
-def shorten_verilog(path: str) -> None:
+def shorten_verilog(path: str, *, limit: int = VERILATOR_LIMIT) -> None:
     """Shorten escaped identifiers in a Verilog file in-place."""
     with open(path) as f:
         original = f.read()
 
-    id_map = build_id_map(original)
+    id_map = build_id_map(original, limit=limit)
 
     if not id_map:
-        print(f'No identifiers reach {VERILATOR_LIMIT}-char limit in {path}')
+        print(f'No identifiers reach {limit}-char limit in {path}')
         return
 
     escaped_re = re.compile(r'\\([^ \t\n;,)(]+)')
@@ -126,15 +126,18 @@ def _replace(m: re.Match) -> str:
 
     with open(path, 'w') as f:
         f.write(shortened)
-    print(f'Shortened {len(id_map)} identifiers in {path} (round-trip OK)')
+    print(f'Shortened {len(id_map)} identifiers in {path} (limit={limit}, round-trip OK)')
 
 
 def main() -> None:
     parser = argparse.ArgumentParser(description=__doc__)
     parser.add_argument('netlist', help='Verilog netlist to process in-place')
+    parser.add_argument('--reserve', type=int, default=0,
+                        help='Reserve N chars for suffixes appended after shortening '
+                             '(effective limit = VERILATOR_LIMIT - reserve)')
     args = parser.parse_args()
 
-    shorten_verilog(args.netlist)
+    shorten_verilog(args.netlist, limit=VERILATOR_LIMIT - args.reserve)
 
 
 if __name__ == '__main__':

hw/ip/otbn/pre_sca/alma/verify_mai.sh

@@ -33,16 +33,16 @@ case "$TARGET_TYPE" in
 esac
 export TOP_MODULE
 
-echo "Verifying ${TOP_MODULE} using Alma"
+echo "Verifying ${TOP_MODULE} using CocoAlma"
 
-# Pre-process alma.v: flatten all sub-module instances first so that parse.py's
-# own 'flatten' step has nothing left to inline (preventing it from creating new
-# long hierarchical signal names at that stage).  Then shorten every escaped
-# identifier whose C++ length exceeds Verilator's ~128-char limit in one pass.
+# Pre-process alma.v: shorten escaped identifiers whose C++ length exceeds
+# VERILATOR_LIMIT - 11.  The 11-char reserve accounts for the longest port
+# suffix that parse.py's internal flatten appends to kept prim_* instance names
+# ('.out_o_n' from prim_xnor2: 4 cpp-chars for the dot + 7 chars = 11).
 ALMA_V="${REPO_TOP}/hw/ip/otbn/pre_syn/syn_out/latest/generated/${TOP_MODULE}.alma.v"
 ALMA_FLAT="${REPO_TOP}/hw/ip/otbn/pre_syn/syn_out/latest/generated/${TOP_MODULE}.alma.flat.v"
-yosys -q -p "read_verilog ${ALMA_V}; proc; flatten; clean; write_verilog -noattr ${ALMA_FLAT}"
-python3 ${REPO_TOP}/hw/ip/otbn/pre_sca/alma/shorten_alma_identifiers.py "${ALMA_FLAT}"
+cp "${ALMA_V}" "${ALMA_FLAT}"
+python3 ${REPO_TOP}/hw/ip/otbn/pre_sca/alma/shorten_alma_identifiers.py --reserve 11 "${ALMA_FLAT}"
 
 # Parse
 ./parse.py --top-module ${TOP_MODULE} \