Remove trailing whitespaces

Signed-off-by: Pirmin Vogel <[email protected]>

Author: vogelpi

hw/dv/sv/cip_lib/cip_base_virtual_sequencer.sv

@@ -19,4 +19,3 @@ class cip_base_virtual_sequencer #(type CFG_T = cip_base_env_cfg,
   `uvm_component_new
 
 endclass
-

hw/dv/sv/dv_lib/dv_base_agent.sv

@@ -65,4 +65,3 @@ class dv_base_agent #(type CFG_T            = dv_base_agent_cfg,
   endfunction
 
 endclass
-

hw/dv/sv/dv_lib/dv_base_driver.sv

@@ -34,4 +34,3 @@ class dv_base_driver #(type ITEM_T     = uvm_sequence_item,
   endtask
 
 endclass
-

hw/dv/sv/dv_lib/dv_base_scoreboard.sv

@@ -78,4 +78,3 @@ class dv_base_scoreboard #(type RAL_T = dv_base_reg_block,
   endfunction : pre_abort
 
 endclass
-

hw/dv/sv/pattgen_agent/pattgen_if.sv

@@ -13,4 +13,3 @@ interface pattgen_if #(
   logic [NumChannels-1:0] pcl_tx;
 
 endinterface : pattgen_if
-

hw/dv/sv/tl_agent/dv/tests/tl_agent_base_test.sv

@@ -7,4 +7,3 @@ class tl_agent_base_test extends dv_base_test #(.ENV_T(tl_agent_env), .CFG_T(tl_
   `uvm_component_new
 
 endclass : tl_agent_base_test
-

hw/dv/tools/dvsim/common_modes.hjson

@@ -52,14 +52,14 @@
     // in two ways. One of them is setting the pre-processor macro `BUILD_SEED` to the seed value,
     // which is done below. The SystemVerilog testbench sources can use the `BUILD_SEED` macro
     // value to set some design constants (such as parameters) upon instantiation. The `BUILD_SEED`,
-    // if not set externally (by passing the --build-seed switch) is set to 1 in 
-    // `hw/dv/sv/dv_utils/dv_macros.svh`. The other way is by passing the {seed} value to utility 
-    // scripts that generate packages that contain randomized constants. These utility scripts can 
-    // be invoked as a `pre_build_cmd`, wrapped within the `build_seed` sim mode in the DUT 
+    // if not set externally (by passing the --build-seed switch) is set to 1 in
+    // `hw/dv/sv/dv_utils/dv_macros.svh`. The other way is by passing the {seed} value to utility
+    // scripts that generate packages that contain randomized constants. These utility scripts can
+    // be invoked as a `pre_build_cmd`, wrapped within the `build_seed` sim mode in the DUT
     // simulation configuration Hjson file. All forms of build randomization must be wrapped within
-    // this `build_seed` sim mode. They will all use the same {seed} value, which allows us to 
-    // deterministically reproduce failures. The `--build-seed` switch is expected to be passed 
-    // when running the nightly regressions. The `seed` value set by dvsim is a 32-bit unsigned 
+    // this `build_seed` sim mode. They will all use the same {seed} value, which allows us to
+    // deterministically reproduce failures. The `--build-seed` switch is expected to be passed
+    // when running the nightly regressions. The `seed` value set by dvsim is a 32-bit unsigned
     // integer (unless specified on the command-line).
     {
       name: build_seed

hw/dv/tools/xcelium/unr.cfg

@@ -1,9 +1,9 @@
 # Copyright lowRISC contributors.
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
-check_unr -setup 
+check_unr -setup
 
-#Setup the clock and reset the design 
+#Setup the clock and reset the design
 clock -infer
 reset ~dut.rst_ni
 get_reset_info

hw/formal/tools/vcformal/vcf_dvsim_report.tcl

@@ -42,4 +42,3 @@ proc vcf_dvsim_report { } {
 	echo "${prop_id},assume,${prop_status},${prop_name},${prop_vacuity},,,,"
     }
 }
-

hw/ip/adc_ctrl/dv/env/seq_lib/adc_ctrl_vseq_list.sv

@@ -16,4 +16,3 @@
 `include "adc_ctrl_filters_both_vseq.sv"
 `include "adc_ctrl_clock_gating_vseq.sv"
 `include "adc_ctrl_stress_all_vseq.sv"
-