Guidance Request: understanding OpenTitan flows and using commercial tools #29171
Description
Description
Hello OpenTitan team,
I am new to the OpenTitan project and currently trying to learn and understand the overall development flow from the ground up.
We are exploring OpenTitan as a possible base for a security-focused SoC (such as an HSM), and our immediate goal is to clearly understand how the OpenTitan flows are intended to be used, starting from RTL and progressing step by step.
As a beginner, we are finding it difficult to understand the complete picture by reading the repository alone as there is no enough documentation, and we would really appreciate some guidance from the community.
Specifically, we are trying to understand:
The intended bottom-up flow
How the RTL is expected to be built and verified (packages, primitives, IPs, subsystems, top level)
Which blocks are expected to be worked on or verified individually, and which are only meant to be used at top level
Simulation flow
How the FuseSoC-based flow maps conceptually to IP-level or top-level simulation
Any guidance for users who want to use a commercial simulator instead of the default open-source tools
Lint and CDC
Any architectural guidance that would help when using commercial lint/CDC tools
Synthesis and FPGA bring-up
Compilation list for Xilinx FPGA , Verification environment for FPGA, Synthesis and PnR scripts ,
Generated Xilinx cores Clock ,Memory other modules, Supported Xilinx FPGA Boards
Our intention is not to replace the official flows, but to understand them clearly first, and then carefully adapt or migrate them to commercial tools in a way that stays aligned with OpenTitan’s architecture and intent.
If there are any beginner-oriented documents, presentations, recorded talks, prior discussions, or general advice on how to approach OpenTitan learning step by step, we would be very grateful for pointers.
Thank you very much for your time and for maintaining such an important open-source silicon project.
Best regards,
Partha