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Description
Description
The hardware revision constant in LC_CTRL is currently defined by a SystemVerilog parameter which is then used as is in the design. As a result, synthesis will optimize the parameter into the logic and it's not possible to change the hardware revision number when doing a metal spin. We should add a new primitive cell that is mapped to something like tie cells with synthesis constraints on it to prevent optimizations.
Similarly, we're using prim_sec_anchor_buf primitives for buffering constants inside OTP_CTRL (e.g. static scrambling keys) and KEYMGR (diversification constants). In both cases these are netlist secrets. So we want to ensure that we can track these signals during back end design.
So the task here is to:
- Add a
prim_const_bufand aprim_const_sec_anchor_bufwhere the latter is a wrapper around the former one to ensure the name remains available in the netlist. - Work out the synthesis constraints for these new const buffer cells / tie cells. We want to avoid that multiple such cells get combined into a single one.
- Use those cells in:
- LC_CTRL for the hardware revision
- KEYMGR[_DPE] for netlist constants going through prim_sec_anchor_buf stages
- OTP_CTRL for netlist constants going through prim_sec_anchor_buf stages
- Any other modules?
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