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RISC-V Zbr0p93 support
Signed-off-by: James Wainwright <james.wainwright@lowrisc.org>
1 parent 922d41e commit c5a659c

15 files changed

Lines changed: 340 additions & 2 deletions

‎disas/meson.build‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,8 @@ common_ss.add(when: 'CONFIG_MIPS_DIS', if_true: files('mips.c', 'nanomips.c'))
77
common_ss.add(when: 'CONFIG_RISCV_DIS', if_true: files(
88
'riscv.c',
99
'riscv-xthead.c',
10-
'riscv-xventana.c'
10+
'riscv-xventana.c',
11+
'riscv-zbr.c'
1112
))
1213
common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4.c'))
1314
common_ss.add(when: 'CONFIG_SPARC_DIS', if_true: files('sparc.c'))

‎disas/riscv-zbr-0-93.c‎

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,78 @@
1+
/*
2+
* QEMU RISC-V Disassembler for Zbr v0.93 (unratified)
3+
*
4+
* Copyright (c) 2023 Rivos Inc
5+
*
6+
* SPDX-License-Identifier: GPL-2.0-or-later
7+
*/
8+
9+
#include "qemu/osdep.h"
10+
11+
#include "disas/riscv.h"
12+
#include "disas/riscv-zbr.h"
13+
14+
typedef enum {
15+
/* 0 is reserved for rv_op_illegal. */
16+
rv_op_crc32_b = 1,
17+
rv_op_crc32_h = 2,
18+
rv_op_crc32_w = 3,
19+
rv_op_crc32_d = 4,
20+
rv_op_crc32c_b = 5,
21+
rv_op_crc32c_h = 6,
22+
rv_op_crc32c_w = 7,
23+
rv_op_crc32c_d = 8,
24+
} rv_zbr_op;
25+
26+
const rv_opcode_data rv_zbr_opcode_data[] = {
27+
{ "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
28+
{ "crc32.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
29+
{ "crc32.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
30+
{ "crc32.w", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
31+
{ "crc32.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
32+
{ "crc32c.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
33+
{ "crc32c.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
34+
{ "crc32c.w", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
35+
{ "crc32c.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
36+
};
37+
38+
void decode_zbr(rv_decode *dec, rv_isa isa)
39+
{
40+
rv_inst inst = dec->inst;
41+
rv_opcode op = rv_op_illegal;
42+
43+
switch ((inst >> 0) & 0b1111111) {
44+
case 0b0010011:
45+
switch ((inst >> 12) & 0b111) {
46+
case 0b001:
47+
switch ((inst >> 20 & 0b111111111111)) {
48+
case 0b011000010000:
49+
op = rv_op_crc32_b;
50+
break;
51+
case 0b011000010001:
52+
op = rv_op_crc32_h;
53+
break;
54+
case 0b011000010010:
55+
op = rv_op_crc32_w;
56+
break;
57+
case 0b011000010011:
58+
op = rv_op_crc32_d;
59+
break;
60+
case 0b011000011000:
61+
op = rv_op_crc32c_b;
62+
break;
63+
case 0b011000011001:
64+
op = rv_op_crc32c_h;
65+
break;
66+
case 0b011000011010:
67+
op = rv_op_crc32c_w;
68+
break;
69+
case 0b011000011011:
70+
op = rv_op_crc32c_d;
71+
break;
72+
}
73+
break;
74+
}
75+
break;
76+
}
77+
dec->op = op;
78+
}

‎disas/riscv-zbr-0-93.h‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
/*
2+
* QEMU RISC-V Disassembler for Zbr v0.93 (unratified)
3+
*
4+
* Copyright (c) 2023 Rivos Inc
5+
*
6+
* SPDX-License-Identifier: GPL-2.0-or-later
7+
*/
8+
9+
#ifndef DISAS_RISCV_ZBR_0_93_H
10+
#define DISAS_RISCV_ZBR_0_93_H
11+
12+
#include "disas/riscv.h"
13+
14+
extern const rv_opcode_data rv_zbr_opcode_data[];
15+
16+
void decode_zbr(rv_decode *, rv_isa);
17+
18+
#endif /* DISAS_RISCV_ZBR_0_93_H */

‎disas/riscv-zbr.c‎

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,78 @@
1+
/*
2+
* QEMU RISC-V Disassembler for Zbr v0.93 (unratified)
3+
*
4+
* Copyright (c) 2023 Rivos Inc
5+
*
6+
* SPDX-License-Identifier: GPL-2.0-or-later
7+
*/
8+
9+
#include "qemu/osdep.h"
10+
11+
#include "disas/riscv.h"
12+
#include "disas/riscv-zbr.h"
13+
14+
typedef enum {
15+
/* 0 is reserved for rv_op_illegal. */
16+
rv_op_crc32_b = 1,
17+
rv_op_crc32_h = 2,
18+
rv_op_crc32_w = 3,
19+
rv_op_crc32_d = 4,
20+
rv_op_crc32c_b = 5,
21+
rv_op_crc32c_h = 6,
22+
rv_op_crc32c_w = 7,
23+
rv_op_crc32c_d = 8,
24+
} rv_zbr_op;
25+
26+
const rv_opcode_data rv_zbr_opcode_data[] = {
27+
{ "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
28+
{ "crc32.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
29+
{ "crc32.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
30+
{ "crc32.w", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
31+
{ "crc32.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
32+
{ "crc32c.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
33+
{ "crc32c.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
34+
{ "crc32c.w", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
35+
{ "crc32c.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
36+
};
37+
38+
void decode_zbr(rv_decode *dec, rv_isa isa)
39+
{
40+
rv_inst inst = dec->inst;
41+
rv_opcode op = rv_op_illegal;
42+
43+
switch ((inst >> 0) & 0b1111111) {
44+
case 0b0010011:
45+
switch ((inst >> 12) & 0b111) {
46+
case 0b001:
47+
switch ((inst >> 20 & 0b111111111111)) {
48+
case 0b011000010000:
49+
op = rv_op_crc32_b;
50+
break;
51+
case 0b011000010001:
52+
op = rv_op_crc32_h;
53+
break;
54+
case 0b011000010010:
55+
op = rv_op_crc32_w;
56+
break;
57+
case 0b011000010011:
58+
op = rv_op_crc32_d;
59+
break;
60+
case 0b011000011000:
61+
op = rv_op_crc32c_b;
62+
break;
63+
case 0b011000011001:
64+
op = rv_op_crc32c_h;
65+
break;
66+
case 0b011000011010:
67+
op = rv_op_crc32c_w;
68+
break;
69+
case 0b011000011011:
70+
op = rv_op_crc32c_d;
71+
break;
72+
}
73+
break;
74+
}
75+
break;
76+
}
77+
dec->op = op;
78+
}

‎disas/riscv-zbr.h‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
/*
2+
* QEMU RISC-V Disassembler for Zbr v0.93 (unratified)
3+
*
4+
* Copyright (c) 2023 Rivos Inc
5+
*
6+
* SPDX-License-Identifier: GPL-2.0-or-later
7+
*/
8+
9+
#ifndef DISAS_RISCV_ZBR_H
10+
#define DISAS_RISCV_ZBR_H
11+
12+
#include "disas/riscv.h"
13+
14+
extern const rv_opcode_data rv_zbr_opcode_data[];
15+
16+
void decode_zbr(rv_decode *, rv_isa);
17+
18+
#endif /* DISAS_RISCV_ZBR_H */

‎disas/riscv.c‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,9 @@
2727
#include "disas/riscv-xthead.h"
2828
#include "disas/riscv-xventana.h"
2929

30+
/* Unratified extensions */
31+
#include "disas/riscv-zbr.h"
32+
3033
typedef enum {
3134
/* 0 is reserved for rv_op_illegal. */
3235
rv_op_lui = 1,
@@ -5434,6 +5437,7 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst,
54345437
{ has_xtheadmempair_p, xthead_opcode_data, decode_xtheadmempair },
54355438
{ has_xtheadsync_p, xthead_opcode_data, decode_xtheadsync },
54365439
{ has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondops },
5440+
{ has_zbr_p, rv_zbr_opcode_data, decode_zbr },
54375441
};
54385442

54395443
for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) {

‎target/riscv/bitmanip_helper.c‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,8 @@
2323
#include "exec/target_long.h"
2424
#include "exec/helper-proto.h"
2525
#include "tcg/tcg.h"
26+
#include "qemu/crc32.h"
27+
#include "qemu/crc32c.h"
2628

2729
target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
2830
{
@@ -129,3 +131,21 @@ target_ulong HELPER(xperm8)(target_ulong rs1, target_ulong rs2)
129131
{
130132
return do_xperm(rs1, rs2, 3);
131133
}
134+
135+
target_ulong HELPER(crc32)(target_ulong rs1, target_ulong sz)
136+
{
137+
for (target_ulong i = 0; i < sz; i++) {
138+
rs1 = crc32_table[rs1 & 0xFF] ^ (rs1 >> 8);
139+
}
140+
141+
return rs1;
142+
}
143+
144+
target_ulong HELPER(crc32c)(target_ulong rs1, target_ulong sz)
145+
{
146+
for (target_ulong i = 0; i < sz; i++) {
147+
rs1 = crc32c_table[rs1 & 0xFF] ^ (rs1 >> 8);
148+
}
149+
150+
return rs1;
151+
}

‎target/riscv/cpu.c‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1378,6 +1378,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
13781378
/* These are experimental so mark with 'x-' */
13791379
const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
13801380
MULTI_EXT_CFG_BOOL("x-svukte", ext_svukte, false),
1381+
MULTI_EXT_CFG_BOOL("x-zbr", ext_zbr, false),
13811382

13821383
{ },
13831384
};
@@ -3057,7 +3058,8 @@ static const TypeInfo riscv_cpu_type_infos[] = {
30573058
.cfg.ext_zba = true,
30583059
.cfg.ext_zbb = true,
30593060
.cfg.ext_zbc = true,
3060-
.cfg.ext_zbs = true
3061+
.cfg.ext_zbs = true,
3062+
.cfg.ext_zbr = true
30613063
),
30623064

30633065
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E31, TYPE_RISCV_CPU_SIFIVE_E,

‎target/riscv/cpu_cfg.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -70,4 +70,7 @@ MATERIALISE_EXT_PREDICATE(xtheadmempair)
7070
MATERIALISE_EXT_PREDICATE(xtheadsync)
7171
MATERIALISE_EXT_PREDICATE(XVentanaCondOps)
7272

73+
/* Extensions that are not yet upstream */
74+
MATERIALISE_EXT_PREDICATE(zbr);
75+
7376
#endif

‎target/riscv/cpu_cfg_fields.h.inc‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@ BOOL_FIELD(ext_zbc)
1111
BOOL_FIELD(ext_zbkb)
1212
BOOL_FIELD(ext_zbkc)
1313
BOOL_FIELD(ext_zbkx)
14+
BOOL_FIELD(ext_zbr)
1415
BOOL_FIELD(ext_zbs)
1516
BOOL_FIELD(ext_zca)
1617
BOOL_FIELD(ext_zcb)

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