Support execution disablement

[rivos-eblot]

Some device such as the SRAM controller or the Flash controller may disable instruction fetch while leaving data access.

This needs to be emulated in QEMU.

The most important show stopper for this feature is that the instruction vs. data information is not available outside the vCPU, and forwarding this information down to the devices would require massive QEMU modifications which would hamper any future downstream integrations.

Until this information is available at device level (i.e. in memory APIs), we need to find a ... creative solution.

[rivos-eblot]

It should be possible to implement execution disablement based on the new ot_vmapper device, which uses the QEMU MMU API and replace the RISC-V MMU with a simplified version that handles address translation and has access to the instruction/data bits.

See #155

[rivos-eblot]

It has been successfully implemented with ot_vmapper. Need to back port this feature from the Darjeeling branch to the current EarlGrey branch.