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feat(mapper-199): align bank_values_ext init defaults with Mesen2/FCEUX
Initialize CHR slots 1 and 3 (driven by exReg[2] / exReg[3], stored in bank_values_ext[2] / bank_values_ext[3]) to bank values 1 and 3 respectively at construction time. Without this, the slots default to bank 0 -- so any CHR read between Txrom::new() and the game's $8001 init writes would render slots 1 and 3 from CHR-RAM bank 0 instead of banks 1 and 3. In practice every observed mapper-199 ROM (Sangokushi II, Dragon Ball Z 2 / Gaiden, etc.) overwrites these registers immediately during boot via ctrl0=A and ctrl0=B writes, so this is defensive alignment, not a gameplay fix. If post-fix testing shows behavior is unchanged, this commit can be squashed into the mapper 199 feature commit. Cross-verified against the references: * Mesen2 (Mmc3Variants/MMC3_199.h InitMapper): _exRegs[2] = 1; _exRegs[3] = 3; * FCEUX (boards/199.cpp M199Power): EXPREGS[2] = 1; EXPREGS[3] = 3; Signed-off-by: Kefu Chai <tchaikov@gmail.com>
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Lines changed: 8 additions & 3 deletions

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tetanes-core/src/mapper/m004_txrom.rs

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -145,11 +145,16 @@ impl Txrom {
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};
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let last_bank = txrom.prg_rom_banks.last();
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if txrom.mapper_num == 199 {
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// TypeG default: exPrg[2]=last-1 ($C000), exPrg[3]=last ($E000). These are the same
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// as the standard MMC3 fixed-bank defaults, but they're written via exPrg so we init
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// bank_values_ext accordingly. The game will overwrite via ctrl0=8 and ctrl0=9 writes.
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// TypeG hardware power-on defaults:
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// exPrg[2]=last-1 ($C000), exPrg[3]=last ($E000) -- same as standard MMC3 fixed
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// banks, but written via exPrg in TypeG.
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// exChr[1]=1, exChr[3]=3 -- CHR slots 1 and 3 default to CHR-RAM banks 1 and 3
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// (banks < 8 redirect to ext_vram). The game overwrites these via ctrl0=A/B,
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// but defaults must be sane in case anything reads CHR before init.
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txrom.regs.bank_values_ext[0] = (last_bank - 1) as u8; // exPrg[2]
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txrom.regs.bank_values_ext[1] = last_bank as u8; // exPrg[3]
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txrom.regs.bank_values_ext[2] = 1; // exChr[1]
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txrom.regs.bank_values_ext[3] = 3; // exChr[3]
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}
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txrom.prg_rom_banks.set(2, last_bank - 1);
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txrom.prg_rom_banks.set(3, last_bank);

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