Commit e222fd7
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PCIe NUMA topology: support cross-NUMA device placement
On NVIDIA GB200 Grace Blackwell systems, GPUs are on separate NUMA
nodes from all CPUs by design. A 2-superchip GB200 exposes:
NUMA 0: Grace CPU kubevirt#1 (CPUs 0-71, ~490 GB LPDDR5X)
NUMA 1: Grace CPU kubevirt#2 (CPUs 72-143, ~490 GB LPDDR5X)
NUMA 2: Blackwell GPU kubevirt#1 (no CPUs, ~188 GB HBM)
NUMA 10: Blackwell GPU kubevirt#2 (no CPUs, ~188 GB HBM)
The existing PCIe NUMA-aware topology code discovers the host NUMA node
for each passthrough device but discards it when no vCPUs are pinned to
that node, causing the device to fall back to the default pci.0 bus
without NUMA affinity information.
Extend LookupDevicesNumaNodes to return both aligned devices (host NUMA
node has pinned vCPUs) and unaligned devices (host NUMA node has no
pinned vCPUs but is a valid NUMA node). When the expander bus assigner
encounters an unaligned device, it creates a CPU-less guest NUMA cell
for the device's host NUMA node and places the device under a
pcie-expander-bus targeting that cell.
On a GB200 each GPU naturally gets its own expander bus and SMMUv3 IOMMU
device through the standard per-NUMA topology path, since each GPU is
on its own NUMA node.
Also adds an explicit check for NUMA node -1 in GetDeviceNumaNode to
avoid relying on uint32 overflow for devices without NUMA affinity.
Ref: https://docs.nvidia.com/dccpu/grace-perf-tuning-guide/system.html
Assisted-By: Claude <noreply@anthropic.com>
Signed-off-by: Lee Yarwood <lyarwood@redhat.com>1 parent 42435eb commit e222fd7
4 files changed
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