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| 1 | +library IEEE; |
| 2 | +use IEEE.std_logic_1164.all; -- defines std_logic types |
| 3 | +use IEEE.STD_LOGIC_ARITH.ALL; |
| 4 | +use IEEE.STD_LOGIC_UNSIGNED.ALL; |
| 5 | + |
| 6 | +-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics |
| 7 | +-- http://www.mesanet.com |
| 8 | +-- |
| 9 | +-- Ported to MYIR ZTURN IO Carrier board: |
| 10 | +-- Copyright (C) 2016, Devin Hughes, JD Squared |
| 11 | +-- http://www.jd2.com |
| 12 | +-- |
| 13 | +-- This program is is licensed under a disjunctive dual license giving you |
| 14 | +-- the choice of one of the two following sets of free software/open source |
| 15 | +-- licensing terms: |
| 16 | +-- |
| 17 | +-- * GNU General Public License (GPL), version 2.0 or later |
| 18 | +-- * 3-clause BSD License |
| 19 | +-- |
| 20 | +-- |
| 21 | +-- The GNU GPL License: |
| 22 | +-- |
| 23 | +-- This program is free software; you can redistribute it and/or modify |
| 24 | +-- it under the terms of the GNU General Public License as published by |
| 25 | +-- the Free Software Foundation; either version 2 of the License, or |
| 26 | +-- (at your option) any later version. |
| 27 | +-- |
| 28 | +-- This program is distributed in the hope that it will be useful, |
| 29 | +-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 30 | +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 31 | +-- GNU General Public License for more details. |
| 32 | +-- |
| 33 | +-- You should have received a copy of the GNU General Public License |
| 34 | +-- along with this program; if not, write to the Free Software |
| 35 | +-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 36 | +-- |
| 37 | +-- |
| 38 | +-- The 3-clause BSD License: |
| 39 | +-- |
| 40 | +-- Redistribution and use in source and binary forms, with or without |
| 41 | +-- modification, are permitted provided that the following conditions |
| 42 | +-- are met: |
| 43 | +-- |
| 44 | +-- * Redistributions of source code must retain the above copyright |
| 45 | +-- notice, this list of conditions and the following disclaimer. |
| 46 | +-- |
| 47 | +-- * Redistributions in binary form must reproduce the above |
| 48 | +-- copyright notice, this list of conditions and the following |
| 49 | +-- disclaimer in the documentation and/or other materials |
| 50 | +-- provided with the distribution. |
| 51 | +-- |
| 52 | +-- * Neither the name of Mesa Electronics nor the names of its |
| 53 | +-- contributors may be used to endorse or promote products |
| 54 | +-- derived from this software without specific prior written |
| 55 | +-- permission. |
| 56 | +-- |
| 57 | +-- |
| 58 | +-- Disclaimer: |
| 59 | +-- |
| 60 | +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 61 | +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 62 | +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 63 | +-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 64 | +-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 65 | +-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 66 | +-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 67 | +-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| 68 | +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 69 | +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
| 70 | +-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 71 | +-- POSSIBILITY OF SUCH DAMAGE. |
| 72 | +-- |
| 73 | + |
| 74 | +use work.IDROMConst.all; |
| 75 | + |
| 76 | +package PIN_KR260_36 is |
| 77 | + constant ModuleID : ModuleIDType :=( |
| 78 | + (HM2DPLLTag, x"00", ClockLowTag, x"04", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask), |
| 79 | + (IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask), |
| 80 | + (QcountTag, x"02", ClockLowTag, x"02", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask), |
| 81 | + (StepGenTag, x"02", ClockLowTag, x"08", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask), |
| 82 | + (FWIDTag, x"00", ClockLowTag, x"01", FWIDAddr&PadT, FWIDNumRegs, x"00", FWIDMPBitMask), |
| 83 | + (PWMTag, x"00", ClockHighTag, x"03", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask), |
| 84 | + (LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask), |
| 85 | + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), |
| 86 | + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), |
| 87 | + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), |
| 88 | + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), |
| 89 | + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), |
| 90 | + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), |
| 91 | + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), |
| 92 | + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), |
| 93 | + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), |
| 94 | + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), |
| 95 | + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), |
| 96 | + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), |
| 97 | + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), |
| 98 | + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), |
| 99 | + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), |
| 100 | + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), |
| 101 | + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), |
| 102 | + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), |
| 103 | + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), |
| 104 | + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), |
| 105 | + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), |
| 106 | + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), |
| 107 | + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), |
| 108 | + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), |
| 109 | + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000") |
| 110 | + ); |
| 111 | + |
| 112 | + |
| 113 | + constant PinDesc : PinDescType :=( |
| 114 | + -- Base func sec unit sec func sec pin -- hostmot2 Header Pin Func HD = 3V3, SD = 1V8 |
| 115 | + IOPortTag & x"00" & NullTag & NullPin, -- I/O 00 HD_GPIO0_0 J15_11 GPIO |
| 116 | + IOPortTag & x"00" & NullTag & NullPin, -- I/O 01 HD_GPIO0_1 J15_12 GPIO |
| 117 | + IOPortTag & x"00" & NullTag & NullPin, -- I/O 02 HD_GPIO0_2 J15_13 GPIO |
| 118 | + IOPortTag & x"00" & NullTag & NullPin, -- I/O 03 HD_GPIO0_3 J15_14 GPIO |
| 119 | + IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 04 HD_GPIO0_4 J15_15 A Dir |
| 120 | + IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 05 HD_GPIO0_5 J15_16 A Step |
| 121 | + IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 06 HD_GPIO0_6 J15_17 B Dir |
| 122 | + IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 07 HD_GPIO0_7 J15_18 B Step |
| 123 | + IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 08 HD_GPIO0_8 J16_21 C Dir |
| 124 | + IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 09 HD_GPIO0_9 J16_22 C Step |
| 125 | + IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 10 HD_GPIO0_10 J16_23 D Dir |
| 126 | + IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 11 HD_GPIO0_11 J16_24 D Step |
| 127 | + IOPortTag & x"00" & HM2DPLLTag & HM2DPLLRefOutPin, -- I/O 12 HD_GPIO0_12 J16_25 DPLL Ref Output |
| 128 | + IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 13 HD_GPIO0_14 J16_26 Input 1 (Quad A) |
| 129 | + IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 14 HD_GPIO0_14 J16_27 Input 2 (Quad B) |
| 130 | + IOPortTag & x"00" & QCountTag & QCountIdxPin, -- I/O 15 HD_GPIO0_15 J16_28 Input 3 (Quad Idx) |
| 131 | + |
| 132 | + -- Base func sec unit sec func sec pin -- hostmot2 Header Pin Func |
| 133 | + IOPortTag & x"00" & NullTag & NullPin, -- I/O 16 HD_GPIO0_16 J16_31 GPIO |
| 134 | + IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 17 HD_GPIO0_17 J16_32 PWM |
| 135 | + IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 18 HD_GPIO0_18 J16_33 PWM |
| 136 | + IOPortTag & x"02" & PWMTag & PWMAOutPin, -- I/O 19 HD_GPIO0_19 J16_34 PWM |
| 137 | + IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 20 HD_GPIO0_20 J16_35 E Dir |
| 138 | + IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 21 HD_GPIO0_21 J16_36 E Step |
| 139 | + IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 22 HD_GPIO0_22 J16_37 F Dir |
| 140 | + IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 23 HD_GPIO0_23 J16_38 F Step |
| 141 | + IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 24 SD_GPIO0_24 J15_21 G Dir |
| 142 | + IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 25 SD_GPIO0_25 J15_22 G Step |
| 143 | + IOPortTag & x"07" & StepGenTag & StepGenDirPin, -- I/O 26 SD_GPIO0_26 J15_23 H Dir |
| 144 | + IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 27 SD_GPIO0_27 J15_24 H Step |
| 145 | + IOPortTag & x"00" & NullTag & NullPin, -- I/O 28 SD_GPIO0_28 J15_25 GPIO |
| 146 | + IOPortTag & x"00" & NullTag & NullPin, -- I/O 29 SD_GPIO0_29 J15_26 GPIO |
| 147 | + IOPortTag & x"00" & NullTag & NullPin, -- I/O 30 SD_GPIO0_30 J15_27 GPIO |
| 148 | + IOPortTag & x"00" & NullTag & NullPin, -- I/O 31 SD_GPIO0_31 J15_28 GPIO |
| 149 | + IOPortTag & x"00" & NullTag & NullPin, -- I/O 32 SD_GPIO0_32 J15_31 GPIO |
| 150 | + IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 33 SD_GPIO0_33 J15_32 Input 1 (Quad A) |
| 151 | + IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 34 SD_GPIO0_34 J15_33 Input 2 (Quad B) |
| 152 | + IOPortTag & x"01" & QCountTag & QCountIdxPin, -- I/O 35 SD_GPIO0_35 J15_34 Input 3 (Quad Idx) |
| 153 | + |
| 154 | + -- Fill remaining 144 pins |
| 155 | + emptypin,emptypin,emptypin,emptypin, |
| 156 | + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, |
| 157 | + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, |
| 158 | + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, |
| 159 | + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, |
| 160 | + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, |
| 161 | + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, |
| 162 | + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, |
| 163 | + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, |
| 164 | + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, |
| 165 | + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, |
| 166 | + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, |
| 167 | + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, |
| 168 | + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin); |
| 169 | + |
| 170 | +end package PIN_KR260_36; |
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