wb_bridge_top.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
use work.miim_types.all;
use work.audioclks_pkg.all;
use work.system_cfg_pkg.all;
ENTITY wb_bridge_top IS
generic (
    	syscfg : t_global_system_cfg := global_system_cfg_cyc

	);
	
	PORT
	(
		rst_n_i :  IN  STD_LOGIC;
		clock_i :  IN  STD_LOGIC;

		-- rgmii if (use when ethernet_type  = RGMII)
		phy_refclk_i :  IN  STD_LOGIC := '0';
		phy_mii_enet_rx_clk :  IN  STD_LOGIC  := '0';
		phy_mii_enet_rx_dv :  IN  STD_LOGIC := '0';
		phy_mii_enet_resetn :  OUT  STD_LOGIC := '0';
		phy_mii_enet_rx_d :  IN  STD_LOGIC_VECTOR(syscfg.PHY_CONFIG.NETWORK_CONFIG.MII_WIDTH - 1 DOWNTO 0)  := (others => '0');
		phy_mii_enet_tx_clk :  OUT  STD_LOGIC  := '0';
        phy_mii_enet_tx_clk_i :  IN  STD_LOGIC  := '0';
		phy_mii_enet_tx_en :  OUT  STD_LOGIC := '0';
		phy_mii_enet_tx_d :  OUT  STD_LOGIC_VECTOR(syscfg.PHY_CONFIG.NETWORK_CONFIG.MII_WIDTH - 1 DOWNTO 0) := (others => '0');

		enet_mdc :  OUT  STD_LOGIC;
		enet_mdio :  INOUT  STD_LOGIC;




		-- audio clock in from external pll - only used when USE_EXTERNAL_PLL is true
		pll_512fs_i :  IN  STD_LOGIC := '0'; -- gpio 1

		-- audio clocks outputs
		audioclocks_o : out t_audio_clocks;
		vcxo_clk_i : IN STD_LOGIC := '0';
		vcxo_pump_o : OUT t_vcxo_pump;
		pin_audioclocks_o : OUT t_audio_clocks;
        selected_audio_clock_o : out t_audio_clocks_selected;
		

		tdm_in :  IN  STD_LOGIC_VECTOR(syscfg.AUDIO_CONFIG.TX_AD_CFG.TDM_PINS - 1 downto 0);
		tdm_out :  OUT  STD_LOGIC_VECTOR(syscfg.AUDIO_CONFIG.RX_DA_CFG.TDM_PINS - 1 downto 0);
		


        rx_sample_register : OUT STD_LOGIC_VECTOR((syscfg.AUDIO_CONFIG.PARALLEL_BYTE_DEPTH * 8) * syscfg.AUDIO_CONFIG.RX_DA_CFG.CHANNELS - 1 downto 0);
        tx_sample_register : IN STD_LOGIC_VECTOR((syscfg.AUDIO_CONFIG.PARALLEL_BYTE_DEPTH * 8) * syscfg.AUDIO_CONFIG.TX_AD_CFG.CHANNELS - 1 downto 0) := (others => '0');
		
		
		mcu_clk_o : OUT std_logic;
        mcu_clk_90_o : OUT std_logic;
        mcu_irq_o : OUT STD_LOGIC;


        -- wishbone bus
      aes67_wb_ack                              : out std_logic;
      aes67_wb_adr                              : in std_logic_vector(29 downto 0);
      aes67_wb_bte                              : in std_logic_vector(1 downto 0);
      aes67_wb_cti                              : in std_logic_vector(2 downto 0);
      aes67_wb_cyc                              : in std_logic;
      aes67_wb_dat_r                            : out std_logic_vector(31 downto 0);
      aes67_wb_dat_w                            : in std_logic_vector(31 downto 0);
      aes67_wb_err                              : out std_logic;
      aes67_wb_sel                              : in std_logic_vector(3 downto 0);
      aes67_wb_stb                              : in std_logic;
      aes67_wb_we                               : in std_logic;
      dbg_mac_tx_clk_o : out std_logic
	);
END wb_bridge_top;

architecture rtl of wb_bridge_top is

signal sys_clk_125MHz : std_logic;
signal mcu_clk : std_logic;

signal mac_speed_i             : std_logic_vector(1 downto 0);
signal mii_rx_clock          : std_logic;
signal mii_tx_clock          : std_logic;
signal mii_rx_err            : std_logic;
signal mii_rx_dv             : std_logic;
signal mii_rxd               : std_logic_vector(7 downto 0);
signal mii_tx_err            : std_logic;
signal mii_tx_en             : std_logic;
signal mii_txd               : std_logic_vector(7 downto 0);
signal rst_n : std_logic;
signal sysclk_pll_locked : std_logic;
signal phy_mii_enet_tx_d_sig : std_logic_vector(syscfg.PHY_CONFIG.NETWORK_CONFIG.MII_WIDTH - 1 downto 0);
signal phy_mii_enet_rx_d_sig : std_logic_vector(syscfg.PHY_CONFIG.NETWORK_CONFIG.MII_WIDTH - 1 downto 0);

signal phy_mii_enet_tx_en_sig : std_logic;
signal phy_rxclk : std_logic;
signal phy_txclk: std_logic;
begin
    rst_n <= rst_n_i and sysclk_pll_locked;
    phy_mii_enet_tx_d <= phy_mii_enet_tx_d_sig;
    phy_mii_enet_rx_d_sig <= phy_mii_enet_rx_d;
    phy_mii_enet_tx_en <= phy_mii_enet_tx_en_sig;

aes67_wb_bridge_inst: entity work.aes67_wb_bridge
 generic map(
    syscfg => syscfg
)
 port map(
    sys_clk_125MHz_i => sys_clk_125MHz,
    enet_clk_i => mii_rx_clock,
    clk_mcu_i => mcu_clk,
    rst_n => rst_n,
    phy_mii_rx_clk_in => phy_rxclk,
    phy_mii_tx_clk_in => phy_txclk,
    phy_mii_tx_data_in => phy_mii_enet_tx_d_sig(syscfg.PHY_CONFIG.NETWORK_CONFIG.MII_WIDTH -1 downto 0),
    phy_mii_rx_data_in => phy_mii_enet_rx_d_sig(syscfg.PHY_CONFIG.NETWORK_CONFIG.MII_WIDTH -1 downto 0),
    phy_mii_tx_en_i => phy_mii_enet_tx_en_sig,
    phy_mii_rx_en_i => phy_mii_enet_rx_dv,
    mii_rx_clock_i => mii_rx_clock,
    mii_tx_clock_i => mii_tx_clock,
    mii_rx_err_i => mii_rx_err,
    mii_rx_dv_i => mii_rx_dv,
    mii_rxd_i => mii_rxd,
    mii_tx_err_o => mii_tx_err,
    mii_tx_en_o => mii_tx_en,
    mii_txd_o => mii_txd,
    enet_mdio => enet_mdio,
    enet_mdc => enet_mdc,
    pll_512fs_i => pll_512fs_i,
    audioclocks_o => audioclocks_o,
    vcxo_clk_i => vcxo_clk_i,
    vcxo_pump_o => vcxo_pump_o,
    pin_audioclocks_o => pin_audioclocks_o,
    selected_audio_clock_o => selected_audio_clock_o,
    aes67_wb_ack => aes67_wb_ack,
    aes67_wb_adr => aes67_wb_adr,
    aes67_wb_bte => aes67_wb_bte,
    aes67_wb_cti => aes67_wb_cti,
    aes67_wb_cyc => aes67_wb_cyc,
    aes67_wb_dat_r => aes67_wb_dat_r,
    aes67_wb_dat_w => aes67_wb_dat_w,
    aes67_wb_err => aes67_wb_err,
    aes67_wb_sel => aes67_wb_sel,
    aes67_wb_stb => aes67_wb_stb,
    aes67_wb_we => aes67_wb_we,
    tdm_out => tdm_out,
    rx_sample_register => rx_sample_register,
    tdm_in => tdm_in,
    tx_sample_register => tx_sample_register,
    eth_irq_o => mcu_irq_o,
    dbg_mac_tx_clk_o => dbg_mac_tx_clk_o
);

  sysclk_pll_gen_inst: entity work.sysclk_pll_gen
   generic map(
      platform => syscfg.PLATFORM,
      clk_in_speed => syscfg.CLK_IN_SPEED
  )
   port map(
      clock_i => clock_i,
      rst_n_i => rst_n_i,
      sys_clk_125MHz_o => sys_clk_125MHz,
      mcu_clk_o => mcu_clk,
      mcu_clk2_o => mcu_clk_90_o,
      locked_o => sysclk_pll_locked
  );
  mcu_clk_o <= mcu_clk;
  mii_converters_inst: entity work.mii_converters
   generic map(
      MII_WIDTH => syscfg.PHY_CONFIG.NETWORK_CONFIG.MII_WIDTH,
      MII_TYPE => syscfg.PHY_CONFIG.NETWORK_CONFIG.MII_TYPE,
      PLATFORM => syscfg.PLATFORM
  )
   port map(
      rst_n_i => rst_n,
      phy_refclk_i => phy_refclk_i,
      phy_mii_enet_rx_clk => phy_mii_enet_rx_clk,
      phy_mii_enet_rx_dv => phy_mii_enet_rx_dv,
      phy_mii_enet_rx_err => '0',
      phy_mii_enet_resetn => phy_mii_enet_resetn,
      phy_mii_enet_rx_d => phy_mii_enet_rx_d,
      phy_mii_enet_tx_clk => phy_mii_enet_tx_clk,
      phy_mii_enet_tx_clk_i => phy_mii_enet_tx_clk_i,
      phy_mii_enet_tx_en => phy_mii_enet_tx_en_sig,
      phy_mii_enet_tx_d => phy_mii_enet_tx_d_sig,
      phy_clk_rx_o => phy_rxclk,
      phy_clk_tx_o => phy_txclk,
      mac_speed_i => mac_speed_i,
      mii_rx_clock_o => mii_rx_clock,
      mii_tx_clock_o => mii_tx_clock,
      mii_rx_err_o => mii_rx_err,
      mii_rx_dv_o => mii_rx_dv,
      mii_rxd_o => mii_rxd,
      mii_tx_err_i => mii_tx_err,
      mii_tx_en_i => mii_tx_en,
      mii_txd_i => mii_txd
  );

end architecture;