Bug 1656226 - Implement the experimental opcodes. r=jseward

Implement some of the experimental SIMD opcodes that are supported by
all of V8, LLVM, and Binaryen, for maximum compatibility with test
content we might be exposed to.  Most/all of these will probably make
it into the spec, as they lead to substantial speedups in some
programs, and they are deterministic.

For spec and cpu mapping details, see:

WebAssembly/simd#122 (pmax/pmin)
WebAssembly/simd#232 (rounding)
WebAssembly/simd#127 (dot product)
WebAssembly/simd#237 (load zero)

The wasm bytecode values used here come from the binaryen changes that
are linked from those tickets, that's the best documentation right
now.  Current binaryen opcode mappings are here:
https://github.com/WebAssembly/binaryen/blob/master/src/wasm-binary.h

Also: Drive-by fix for signatures of vroundss and vroundsd, these are
unary operations and should follow the conventions for these with
src/dest arguments, not src0/src1/dest.

Also: Drive-by fix to add variants of vmovss and vmovsd on x64 that
take Operand source and FloatRegister destination.

Differential Revision: https://phabricator.services.mozilla.com/D85982

UltraBlame original commit: 2d73a015caaa3e70c175172158a6548625dc6da3

Author: marco-c

js/src/jit-test/lib/wasm-binary.js

@@ -234,6 +234,11 @@ F64Code
 0x7c
 ;
 const
+V128Code
+=
+0x7b
+;
+const
 AnyFuncCode
 =
 0x70
@@ -296,6 +301,11 @@ SelectCode
 0x1b
 ;
 const
+LocalGetCode
+=
+0x20
+;
+const
 I32Load
 =
 0x28
@@ -535,6 +545,105 @@ RefFuncCode
 =
 0xd2
 ;
+/
+/
+SIMD
+opcodes
+const
+V128LoadCode
+=
+0x00
+;
+const
+V128StoreCode
+=
+0x0b
+;
+/
+/
+Experimental
+SIMD
+opcodes
+as
+of
+August
+2020
+.
+const
+I32x4DotSI16x8Code
+=
+0xba
+;
+const
+F32x4CeilCode
+=
+0xd8
+;
+const
+F32x4FloorCode
+=
+0xd9
+;
+const
+F32x4TruncCode
+=
+0xda
+;
+const
+F32x4NearestCode
+=
+0xdb
+;
+const
+F64x2CeilCode
+=
+0xdc
+;
+const
+F64x2FloorCode
+=
+0xdd
+;
+const
+F64x2TruncCode
+=
+0xde
+;
+const
+F64x2NearestCode
+=
+0xdf
+;
+const
+F32x4PMinCode
+=
+0xea
+;
+const
+F32x4PMaxCode
+=
+0xeb
+;
+const
+F64x2PMinCode
+=
+0xf6
+;
+const
+F64x2PMaxCode
+=
+0xf7
+;
+const
+V128Load32ZeroCode
+=
+0xfc
+;
+const
+V128Load64ZeroCode
+=
+0xfd
+;
 const
 FirstInvalidOpcode
 =
@@ -1925,6 +2034,18 @@ name
 )
 )
 ;
+if
+(
+exp
+.
+hasOwnProperty
+(
+"
+funcIndex
+"
+)
+)
+{
 body
 .
 push
@@ -1954,6 +2075,60 @@ funcIndex
 )
 ;
 }
+else
+if
+(
+exp
+.
+hasOwnProperty
+(
+"
+memIndex
+"
+)
+)
+{
+body
+.
+push
+(
+.
+.
+.
+varU32
+(
+MemoryCode
+)
+)
+;
+body
+.
+push
+(
+.
+.
+.
+varU32
+(
+exp
+.
+memIndex
+)
+)
+;
+}
+else
+{
+throw
+"
+Bad
+export
+"
++
+exp
+;
+}
+}
 return
 {
 name

js/src/jit-test/tests/wasm/binary.js

@@ -4078,7 +4078,6 @@ reservedSimd
 0xb2
 0xb3
 0xb4
-0xba
 0xbb
 0xbc
 0xbd
@@ -4101,6 +4100,35 @@ reservedSimd
 0xd4
 0xd6
 0xd7
+0xee
+0xfe
+0xff
+/
+/
+These
+are
+experimental
+opcodes
+currently
+we
+support
+them
+but
+they
+/
+/
+may
+disappear
+again
+.
+/
+/
+0xba
+;
+dot
+product
+/
+/
 0xd8
 0xd9
 0xda
@@ -4109,15 +4137,27 @@ reservedSimd
 0xdd
 0xde
 0xdf
+;
+rounding
+/
+/
 0xea
 0xeb
-0xee
 0xf6
 0xf7
+;
+pseudo
+min
+/
+max
+/
+/
 0xfc
 0xfd
-0xfe
-0xff
+;
+load
++
+zero
 ]
 ;
 for