-
Notifications
You must be signed in to change notification settings - Fork 1
/
Copy pathethmac_wb.v
172 lines (152 loc) · 7.46 KB
/
ethmac_wb.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
//////////////////////////////////////////////////////////////////
// //
// Ethmac module Wishbone bus width and endian switch //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Arbitrates between two wishbone masters and 13 wishbone //
// slave modules. The ethernet MAC wishbone master is given //
// priority over the Amber core. //
// //
// Author(s): //
// - Conor Santifort, [email protected] //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module ethmac_wb #(
parameter WB_DWIDTH = 32,
parameter WB_SWIDTH = 4
)(
// Ethmac side
input [31:0] i_m_wb_adr,
input [3:0] i_m_wb_sel,
input i_m_wb_we,
output [31:0] o_m_wb_rdat,
input [31:0] i_m_wb_wdat,
input i_m_wb_cyc,
input i_m_wb_stb,
output o_m_wb_ack,
output o_m_wb_err,
// Wishbone arbiter side
output [31:0] o_m_wb_adr,
output [WB_SWIDTH-1:0] o_m_wb_sel,
output o_m_wb_we,
input [WB_DWIDTH-1:0] i_m_wb_rdat,
output [WB_DWIDTH-1:0] o_m_wb_wdat,
output o_m_wb_cyc,
output o_m_wb_stb,
input i_m_wb_ack,
input i_m_wb_err,
// Wishbone arbiter side
input [31:0] i_s_wb_adr,
input [WB_SWIDTH-1:0] i_s_wb_sel,
input i_s_wb_we,
output [WB_DWIDTH-1:0] o_s_wb_rdat,
input [WB_DWIDTH-1:0] i_s_wb_wdat,
input i_s_wb_cyc,
input i_s_wb_stb,
output o_s_wb_ack,
output o_s_wb_err,
// Ethmac side
output [31:0] o_s_wb_adr,
output [3:0] o_s_wb_sel,
output o_s_wb_we,
input [31:0] i_s_wb_rdat,
output [31:0] o_s_wb_wdat,
output o_s_wb_cyc,
output o_s_wb_stb,
input i_s_wb_ack,
input i_s_wb_err
);
`include "system_functions.v"
// =========================
// Master interface - with endian conversion
// =========================
generate
if (WB_DWIDTH == 128)
begin : wbm128
assign o_m_wb_rdat = i_m_wb_adr[3:2] == 2'd3 ? endian_x32(i_m_wb_rdat[127:96]) :
i_m_wb_adr[3:2] == 2'd2 ? endian_x32(i_m_wb_rdat[ 95:64]) :
i_m_wb_adr[3:2] == 2'd1 ? endian_x32(i_m_wb_rdat[ 63:32]) :
endian_x32(i_m_wb_rdat[ 31: 0]) ;
assign o_m_wb_sel = i_m_wb_adr[3:2] == 2'd3 ? { endian_x4(i_m_wb_sel), 12'd0} :
i_m_wb_adr[3:2] == 2'd2 ? { 4'd0, endian_x4(i_m_wb_sel), 8'd0} :
i_m_wb_adr[3:2] == 2'd1 ? { 8'd0, endian_x4(i_m_wb_sel), 4'd0} :
{12'd0, endian_x4(i_m_wb_sel) } ;
assign o_m_wb_wdat = i_m_wb_adr[3:2] == 2'd3 ? { endian_x32(i_m_wb_wdat), 96'd0} :
i_m_wb_adr[3:2] == 2'd2 ? {32'd0, endian_x32(i_m_wb_wdat), 64'd0} :
i_m_wb_adr[3:2] == 2'd1 ? {64'd0, endian_x32(i_m_wb_wdat), 32'd0} :
{96'd0, endian_x32(i_m_wb_wdat) } ;
end
else
begin : wbm32
assign o_m_wb_rdat = endian_x32(i_m_wb_rdat);
assign o_m_wb_sel = endian_x4 (i_m_wb_sel);
assign o_m_wb_wdat = endian_x32(i_m_wb_wdat);
end
endgenerate
assign o_m_wb_ack = i_m_wb_ack;
assign o_m_wb_err = i_m_wb_err;
assign o_m_wb_adr = i_m_wb_adr;
assign o_m_wb_we = i_m_wb_we ;
assign o_m_wb_cyc = i_m_wb_cyc;
assign o_m_wb_stb = i_m_wb_stb;
// =========================
// Slave interface - no endian conversion
// =========================
generate
if (WB_DWIDTH == 128)
begin : wbs128
assign o_s_wb_wdat = i_s_wb_adr[3:2] == 2'd3 ? i_s_wb_wdat[127:96] :
i_s_wb_adr[3:2] == 2'd2 ? i_s_wb_wdat[ 95:64] :
i_s_wb_adr[3:2] == 2'd1 ? i_s_wb_wdat[ 63:32] :
i_s_wb_wdat[ 31: 0] ;
assign o_s_wb_sel = i_s_wb_adr[3:2] == 2'd3 ? i_s_wb_sel[15:12] :
i_s_wb_adr[3:2] == 2'd2 ? i_s_wb_sel[11: 8] :
i_s_wb_adr[3:2] == 2'd1 ? i_s_wb_sel[ 7: 4] :
i_s_wb_sel[ 3: 0] ;
assign o_s_wb_rdat = i_s_wb_adr[3:2] == 2'd3 ? { i_s_wb_rdat, 96'd0} :
i_s_wb_adr[3:2] == 2'd2 ? {32'd0, i_s_wb_rdat, 64'd0} :
i_s_wb_adr[3:2] == 2'd1 ? {64'd0, i_s_wb_rdat, 32'd0} :
{96'd0, i_s_wb_rdat } ;
end
else
begin : wbs32
assign o_s_wb_wdat = i_s_wb_wdat;
assign o_s_wb_sel = i_s_wb_sel;
assign o_s_wb_rdat = i_s_wb_rdat;
end
endgenerate
assign o_s_wb_ack = i_s_wb_ack;
assign o_s_wb_err = i_s_wb_err;
assign o_s_wb_adr = i_s_wb_adr;
assign o_s_wb_we = i_s_wb_we ;
assign o_s_wb_cyc = i_s_wb_cyc;
assign o_s_wb_stb = i_s_wb_stb;
endmodule