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STORM_SoC_basic.twx
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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE twReport [
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
twDebug*, twFoot?, twClientInfo?)>
<!ATTLIST twReport version CDATA "10,4">
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
<!ELEMENT twExecVer (#PCDATA)>
<!ELEMENT twCopyright (#PCDATA)>
<!ELEMENT twCmdLine (#PCDATA)>
<!ELEMENT twDesign (#PCDATA)>
<!ELEMENT twPCF (#PCDATA)>
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
<!ELEMENT twDevName (#PCDATA)>
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
<!ELEMENT twSpeedGrade (#PCDATA)>
<!ELEMENT twSpeedVer (#PCDATA)>
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
<!ELEMENT twItemLimit (#PCDATA)>
<!ELEMENT twUnconst EMPTY>
<!ELEMENT twUnconstLimit (#PCDATA)>
<!ELEMENT twEnvVar EMPTY>
<!ATTLIST twEnvVar name CDATA #REQUIRED>
<!ATTLIST twEnvVar description CDATA #REQUIRED>
<!ELEMENT twWarn (#PCDATA)>
<!ELEMENT twInfo (#PCDATA)>
<!ELEMENT twDebug (#PCDATA)>
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
<!ELEMENT twProc (#PCDATA)>
<!ELEMENT twTemp (#PCDATA)>
<!ELEMENT twVolt (#PCDATA)>
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twCycles (twSigConn+)>
<!ATTLIST twCycles twNum CDATA #REQUIRED>
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
<!ELEMENT twSig (#PCDATA)>
<!ELEMENT twDriver (#PCDATA)>
<!ELEMENT twLoad (#PCDATA)>
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
<!ATTLIST twConst twConstType (NET |
NETDELAY |
NETSKEW |
PATH |
DEFPERIOD |
UNCONSTPATH |
DEFPATH |
PATH2SETUP |
UNCONSTPATH2SETUP |
PATHCLASS |
PATHDELAY |
PERIOD |
FREQUENCY |
PATHBLOCK |
OFFSET |
OFFSETIN |
OFFSETINCLOCK |
UNCONSTOFFSETINCLOCK |
OFFSETINDELAY |
OFFSETINMOD |
OFFSETOUT |
OFFSETOUTCLOCK |
UNCONSTOFFSETOUTCLOCK |
OFFSETOUTDELAY |
OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
twEndPtCnt?,
twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
<!ELEMENT twConstName (#PCDATA)>
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
<!ATTLIST twConstHead uID CDATA #IMPLIED>
<!ELEMENT twItemCnt (#PCDATA)>
<!ELEMENT twErrCnt (#PCDATA)>
<!ELEMENT twErrCntEndPt (#PCDATA)>
<!ELEMENT twErrCntSetup (#PCDATA)>
<!ELEMENT twErrCntHold (#PCDATA)>
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
<!ELEMENT twEndPtCnt (#PCDATA)>
<!ELEMENT twPathErrCnt (#PCDATA)>
<!ELEMENT twMinPer (#PCDATA) >
<!ELEMENT twFootnote EMPTY>
<!ATTLIST twFootnote number CDATA #REQUIRED>
<!ELEMENT twMaxDel (#PCDATA)>
<!ELEMENT twMaxFreq (#PCDATA)>
<!ELEMENT twMinOff (#PCDATA)>
<!ELEMENT twMaxOff (#PCDATA)>
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
<!ELEMENT twTIGName (#PCDATA)>
<!ELEMENT twInstantiated (#PCDATA)>
<!ELEMENT twBlocked (#PCDATA)>
<!ELEMENT twRacePathRpt (twRacePath+)>
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
twSimpleMinPath CDATA #IMPLIED>
<!ELEMENT twTotDel (#PCDATA)>
<!ELEMENT twSrc (#PCDATA)>
<!ATTLIST twSrc BELType CDATA #IMPLIED>
<!ELEMENT twDest (#PCDATA)>
<!ATTLIST twDest BELType CDATA #IMPLIED>
<!ELEMENT twDel (#PCDATA)>
<!ELEMENT twSUTime (#PCDATA)>
<!ELEMENT twTotPathDel (#PCDATA)>
<!ELEMENT twClkSkew (#PCDATA)>
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
<!ELEMENT twSlack (#PCDATA)>
<!ELEMENT twDelConst (#PCDATA)>
<!ELEMENT tw2Phase EMPTY>
<!ELEMENT twClkUncert (#PCDATA)>
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
fDCMJit CDATA #IMPLIED
fPhaseErr CDATA #IMPLIED
sEqu CDATA #IMPLIED>
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
<!ELEMENT twPathRptBanner (#PCDATA)>
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
<!ELEMENT twOff (#PCDATA)>
<!ELEMENT twGuaranteed EMPTY>
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
<!ELEMENT twClkDel (#PCDATA)>
<!ELEMENT twClkSrc (#PCDATA)>
<!ELEMENT twClkDest (#PCDATA)>
<!ELEMENT twGuarInSetup (#PCDATA)>
<!ELEMENT twOffSrc (#PCDATA)>
<!ELEMENT twOffDest (#PCDATA)>
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
<!ELEMENT twDataDel (#PCDATA)>
<!ELEMENT twDataSrc (#PCDATA)>
<!ELEMENT twDataDest (#PCDATA)>
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twLogLvls (#PCDATA)>
<!ELEMENT twSrcSite (#PCDATA)>
<!ELEMENT twSrcClk (#PCDATA)>
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
<!ELEMENT twDelInfo (#PCDATA)>
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twSite (#PCDATA)>
<!ELEMENT twDelType (#PCDATA)>
<!ELEMENT twFanCnt (#PCDATA)>
<!ELEMENT twComp (#PCDATA)>
<!ELEMENT twNet (#PCDATA)>
<!ELEMENT twBEL (#PCDATA)>
<!ELEMENT twLogDel (#PCDATA)>
<!ELEMENT twRouteDel (#PCDATA)>
<!ELEMENT twDestClk (#PCDATA)>
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPctLog (#PCDATA)>
<!ELEMENT twPctRoute (#PCDATA)>
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
<!ELEMENT twTimeConst (#PCDATA)>
<!ELEMENT twAbsSlack (#PCDATA)>
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
<!ELEMENT twSkew (#PCDATA)>
<!ELEMENT twDetNet (twNetDel*)>
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
<!ELEMENT twNetDelInfo (#PCDATA)>
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twDetSkewNet (twNetSkew*)>
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
<!ELEMENT twClkSkewLimit EMPTY>
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
<!ELEMENT twConstRollupTable (twConstRollup*)>
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
<!ELEMENT twConstRollup EMPTY>
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
<!ELEMENT twConstList (twConstListItem)*>
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
<!ELEMENT twNotMet EMPTY>
<!ELEMENT twReqVal (#PCDATA)>
<!ELEMENT twActVal (#PCDATA)>
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
<!ELEMENT twConstStats (twConstName)>
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
<!ELEMENT twConstData EMPTY>
<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
best CDATA #IMPLIED requested CDATA #IMPLIED
errors CDATA #IMPLIED
score CDATA #IMPLIED>
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
<!ELEMENT twTimeGrpName (#PCDATA)>
<!ELEMENT twCompList (twCompName+)>
<!ELEMENT twCompName (#PCDATA)>
<!ELEMENT twSigList (twSigName+)>
<!ELEMENT twSigName (#PCDATA)>
<!ELEMENT twBELList (twBELName+)>
<!ELEMENT twBELName (#PCDATA)>
<!ELEMENT twBlockList (twBlockName+)>
<!ELEMENT twBlockName (#PCDATA)>
<!ELEMENT twMacList (twMacName+)>
<!ELEMENT twMacName (#PCDATA)>
<!ELEMENT twPinList (twPinName+)>
<!ELEMENT twPinName (#PCDATA)>
<!ELEMENT twUnmetConstCnt (#PCDATA)>
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
<!ELEMENT twSU2ClkTime (#PCDATA)>
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twH2ClkTime (#PCDATA)>
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
<!ELEMENT twClk2Pad (twDest, twTime)>
<!ELEMENT twTime (#PCDATA)>
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
<!ELEMENT twClk2Out EMPTY>
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
<!ELEMENT twRiseRise (#PCDATA)>
<!ELEMENT twFallRise (#PCDATA)>
<!ELEMENT twRiseFall (#PCDATA)>
<!ELEMENT twFallFall (#PCDATA)>
<!ELEMENT twPad2PadList (twPad2Pad+)>
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffOutTblRow EMPTY>
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
<!ELEMENT twNonDedClk (#PCDATA)>
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
<!ELEMENT twScore (#PCDATA)>
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
<!ELEMENT twPathCnt (#PCDATA)>
<!ELEMENT twNetCnt (#PCDATA)>
<!ELEMENT twConnCnt (#PCDATA)>
<!ELEMENT twPct (#PCDATA)>
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
<!ELEMENT twMaxCombDel (#PCDATA)>
<!ELEMENT twMaxFromToDel (#PCDATA)>
<!ELEMENT twMaxNetDel (#PCDATA)>
<!ELEMENT twMaxNetSkew (#PCDATA)>
<!ELEMENT twMaxInAfterClk (#PCDATA)>
<!ELEMENT twMinInBeforeClk (#PCDATA)>
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
<!ELEMENT twMinOutAfterClk (#PCDATA)>
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
<!ELEMENT twTimestamp (#PCDATA)>
<!ELEMENT twFootnoteExplanation EMPTY>
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
<!ELEMENT twClientName (#PCDATA)>
<!ELEMENT twAttrList (twAttrListItem)*>
<!ELEMENT twAttrListItem (twName, twValue*)>
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twHead anchorID="1"><twExecVer>Release 14.7 Trace (lin64)</twExecVer><twCopyright>Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3 -s 3 -n
3 -fastpaths -xml STORM_SoC_basic.twx STORM_SoC_basic.ncd -o
STORM_SoC_basic.twr STORM_SoC_basic.pcf -ucf STORM_on_MiniSpartan6.ucf
</twCmdLine><twDesign>STORM_SoC_basic.ncd</twDesign><twDesignPath>STORM_SoC_basic.ncd</twDesignPath><twPCF>STORM_SoC_basic.pcf</twPCF><twPcfPath>STORM_SoC_basic.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="ftg256"><twDevName>xc6slx9</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-3</twSpeedGrade><twSpeedVer>PRODUCTION 1.23 2013-10-13</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="3">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="4">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twConst anchorID="5" twConstType="PERIOD" ><twConstHead uID="1"><twConstName UCFConstName="NET "CLK_I" PERIOD = 20 ns |" ScopeName="">NET "CLK_I_IBUFG" PERIOD = 20 ns HIGH 50%;</twConstName><twItemCnt>1647215</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>15299</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>14.486</twMinPer></twConstHead><twPathRptBanner iPaths="640" iCriticalPaths="0" sType="EndPoint">Paths for end point STORM_TOP_INST/PROCESSOR_CORE/Multishifter/Multiplicator/Mmult_TEMP1 (DSP48_X0Y6.A6), 640 paths
</twPathRptBanner><twPathRpt anchorID="6"><twConstPath anchorID="7" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>5.514</twSlack><twSrc BELType="FF">STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR_0</twSrc><twDest BELType="DSP">STORM_TOP_INST/PROCESSOR_CORE/Multishifter/Multiplicator/Mmult_TEMP1</twDest><twTotPathDel>14.407</twTotPathDel><twClkSkew dest = "0.546" src = "0.590">0.044</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR_0</twSrc><twDest BELType='DSP'>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/Multiplicator/Mmult_TEMP1</twDest><twLogLvls>7</twLogLvls><twSrcSite>SLICE_X19Y6.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK_I_IBUFG_BUFG</twSrcClk><twPathDel><twSite>SLICE_X19Y6.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.391</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR<1></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X5Y13.B2</twSite><twDelType>net</twDelType><twFanCnt>71</twFanCnt><twDelInfo twEdge="twRising">3.000</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR<0></twComp></twPathDel><twPathDel><twSite>SLICE_X5Y13.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/read_access_port_c/ADR_O<4>11</twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mmux_MODE_INT11</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y20.C5</twSite><twDelType>net</twDelType><twFanCnt>14</twFanCnt><twDelInfo twEdge="twRising">1.080</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/MODE_INT<0></twComp></twPathDel><twPathDel><twSite>SLICE_X4Y20.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.204</twDelInfo><twComp>STORM_TOP_INST/I_CACHE_INST/PAGE_BASE_ADR_5<17></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Register_File/read_access_port_b/ADR_O<1>11</twBEL></twPathDel><twPathDel><twSite>SLICE_X5Y17.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.649</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/read_access_port_b/ADR_O<1>1</twComp></twPathDel><twPathDel><twSite>SLICE_X5Y17.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/I_CACHE_INST/PAGE_BASE_ADR_4<18></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Register_File/read_access_port_b/ADR_O<1>14</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y47.C2</twSite><twDelType>net</twDelType><twFanCnt>17</twFanCnt><twDelInfo twEdge="twRising">4.331</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/R_ADR_PORT_B<1></twComp></twPathDel><twPathDel><twSite>SLICE_X12Y47.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.204</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/R_ADR_PORT_B[4]_read_port_6_OUT<23></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE14_RAMC_D1</twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y35.D5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.569</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/R_ADR_PORT_B[4]_read_port_6_OUT<23></twComp></twPathDel><twPathDel><twSite>SLICE_X7Y35.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Memory_Access/BP_BUFFER<27></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O161</twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y31.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.716</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O16</twComp></twPathDel><twPathDel><twSite>SLICE_X7Y31.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/OP_B_REG<24></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O162</twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y31.A5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.187</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O161</twComp></twPathDel><twPathDel><twSite>SLICE_X7Y31.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/OP_B_REG<24></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O163</twBEL></twPathDel><twPathDel><twSite>DSP48_X0Y6.A6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.632</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/OF_OP_B_OUT<23></twComp></twPathDel><twPathDel><twSite>DSP48_X0Y6.CLK</twSite><twDelType>Tdspdck_A_A1REG</twDelType><twDelInfo twEdge="twRising">0.149</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/Multiplicator/Mmult_TEMP1</twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/Multiplicator/Mmult_TEMP1</twBEL></twPathDel><twLogDel>2.243</twLogDel><twRouteDel>12.164</twRouteDel><twTotDel>14.407</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">CLK_I_IBUFG_BUFG</twDestClk><twPctLog>15.6</twPctLog><twPctRoute>84.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="8"><twConstPath anchorID="9" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>6.329</twSlack><twSrc BELType="FF">STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR_0</twSrc><twDest BELType="DSP">STORM_TOP_INST/PROCESSOR_CORE/Multishifter/Multiplicator/Mmult_TEMP1</twDest><twTotPathDel>13.592</twTotPathDel><twClkSkew dest = "0.546" src = "0.590">0.044</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR_0</twSrc><twDest BELType='DSP'>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/Multiplicator/Mmult_TEMP1</twDest><twLogLvls>7</twLogLvls><twSrcSite>SLICE_X19Y6.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK_I_IBUFG_BUFG</twSrcClk><twPathDel><twSite>SLICE_X19Y6.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.391</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR<1></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y14.B2</twSite><twDelType>net</twDelType><twFanCnt>71</twFanCnt><twDelInfo twEdge="twRising">2.207</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR<0></twComp></twPathDel><twPathDel><twSite>SLICE_X4Y14.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.203</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Operation_Flow_Control/INS_BUF_SEL</twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Register_File/read_access_port_b/ADR_O<0>21</twBEL></twPathDel><twPathDel><twSite>SLICE_X6Y20.D3</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.872</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/read_access_port_b/ADR_O<0>_bdd5</twComp></twPathDel><twPathDel><twSite>SLICE_X6Y20.DMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.251</twDelInfo><twComp>STORM_TOP_INST/I_CACHE_INST/ADR_BUF<5></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Register_File/read_access_port_b/ADR_O<1>13</twBEL></twPathDel><twPathDel><twSite>SLICE_X5Y17.B6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.844</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/read_access_port_b/ADR_O<1>12</twComp></twPathDel><twPathDel><twSite>SLICE_X5Y17.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/I_CACHE_INST/PAGE_BASE_ADR_4<18></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Register_File/read_access_port_b/ADR_O<1>14</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y47.C2</twSite><twDelType>net</twDelType><twFanCnt>17</twFanCnt><twDelInfo twEdge="twRising">4.331</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/R_ADR_PORT_B<1></twComp></twPathDel><twPathDel><twSite>SLICE_X12Y47.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.204</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/R_ADR_PORT_B[4]_read_port_6_OUT<23></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE14_RAMC_D1</twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y35.D5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.569</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/R_ADR_PORT_B[4]_read_port_6_OUT<23></twComp></twPathDel><twPathDel><twSite>SLICE_X7Y35.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Memory_Access/BP_BUFFER<27></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O161</twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y31.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.716</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O16</twComp></twPathDel><twPathDel><twSite>SLICE_X7Y31.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/OP_B_REG<24></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O162</twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y31.A5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.187</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O161</twComp></twPathDel><twPathDel><twSite>SLICE_X7Y31.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/OP_B_REG<24></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O163</twBEL></twPathDel><twPathDel><twSite>DSP48_X0Y6.A6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.632</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/OF_OP_B_OUT<23></twComp></twPathDel><twPathDel><twSite>DSP48_X0Y6.CLK</twSite><twDelType>Tdspdck_A_A1REG</twDelType><twDelInfo twEdge="twRising">0.149</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/Multiplicator/Mmult_TEMP1</twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/Multiplicator/Mmult_TEMP1</twBEL></twPathDel><twLogDel>2.234</twLogDel><twRouteDel>11.358</twRouteDel><twTotDel>13.592</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">CLK_I_IBUFG_BUFG</twDestClk><twPctLog>16.4</twPctLog><twPctRoute>83.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="10"><twConstPath anchorID="11" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>6.353</twSlack><twSrc BELType="FF">STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR_0</twSrc><twDest BELType="DSP">STORM_TOP_INST/PROCESSOR_CORE/Multishifter/Multiplicator/Mmult_TEMP1</twDest><twTotPathDel>13.568</twTotPathDel><twClkSkew dest = "0.546" src = "0.590">0.044</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR_0</twSrc><twDest BELType='DSP'>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/Multiplicator/Mmult_TEMP1</twDest><twLogLvls>7</twLogLvls><twSrcSite>SLICE_X19Y6.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK_I_IBUFG_BUFG</twSrcClk><twPathDel><twSite>SLICE_X19Y6.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.391</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR<1></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X5Y13.B2</twSite><twDelType>net</twDelType><twFanCnt>71</twFanCnt><twDelInfo twEdge="twRising">3.000</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR<0></twComp></twPathDel><twPathDel><twSite>SLICE_X5Y13.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/read_access_port_c/ADR_O<4>11</twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mmux_MODE_INT11</twBEL></twPathDel><twPathDel><twSite>SLICE_X2Y18.B3</twSite><twDelType>net</twDelType><twFanCnt>14</twFanCnt><twDelInfo twEdge="twRising">1.542</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/MODE_INT<0></twComp></twPathDel><twPathDel><twSite>SLICE_X2Y18.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.205</twDelInfo><twComp>STORM_TOP_INST/I_CACHE_INST/PAGE_BASE_ADR_4<30></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Register_File/read_access_port_b/ADR_O<4>11</twBEL></twPathDel><twPathDel><twSite>SLICE_X2Y18.D1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.443</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/read_access_port_b/ADR_O<4>1</twComp></twPathDel><twPathDel><twSite>SLICE_X2Y18.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.205</twDelInfo><twComp>STORM_TOP_INST/I_CACHE_INST/PAGE_BASE_ADR_4<30></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Register_File/read_access_port_b/ADR_O<4>13</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y47.C5</twSite><twDelType>net</twDelType><twFanCnt>17</twFanCnt><twDelInfo twEdge="twRising">3.289</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/R_ADR_PORT_B<4></twComp></twPathDel><twPathDel><twSite>SLICE_X12Y47.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.204</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/R_ADR_PORT_B[4]_read_port_6_OUT<23></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE14_RAMC_D1</twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y35.D5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.569</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/R_ADR_PORT_B[4]_read_port_6_OUT<23></twComp></twPathDel><twPathDel><twSite>SLICE_X7Y35.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Memory_Access/BP_BUFFER<27></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O161</twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y31.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.716</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O16</twComp></twPathDel><twPathDel><twSite>SLICE_X7Y31.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/OP_B_REG<24></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O162</twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y31.A5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.187</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O161</twComp></twPathDel><twPathDel><twSite>SLICE_X7Y31.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/OP_B_REG<24></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O163</twBEL></twPathDel><twPathDel><twSite>DSP48_X0Y6.A6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.632</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/OF_OP_B_OUT<23></twComp></twPathDel><twPathDel><twSite>DSP48_X0Y6.CLK</twSite><twDelType>Tdspdck_A_A1REG</twDelType><twDelInfo twEdge="twRising">0.149</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/Multiplicator/Mmult_TEMP1</twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/Multiplicator/Mmult_TEMP1</twBEL></twPathDel><twLogDel>2.190</twLogDel><twRouteDel>11.378</twRouteDel><twTotDel>13.568</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">CLK_I_IBUFG_BUFG</twDestClk><twPctLog>16.1</twPctLog><twPctRoute>83.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="4873" iCriticalPaths="0" sType="EndPoint">Paths for end point VECTOR_INTERRUPT_CONTROLLER/ISR_ADR_2 (SLICE_X21Y44.A4), 4873 paths
</twPathRptBanner><twPathRpt anchorID="12"><twConstPath anchorID="13" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>5.542</twSlack><twSrc BELType="FF">VECTOR_INTERRUPT_CONTROLLER/IRQ_STATUS_5</twSrc><twDest BELType="FF">VECTOR_INTERRUPT_CONTROLLER/ISR_ADR_2</twDest><twTotPathDel>14.315</twTotPathDel><twClkSkew dest = "0.522" src = "0.630">0.108</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>VECTOR_INTERRUPT_CONTROLLER/IRQ_STATUS_5</twSrc><twDest BELType='FF'>VECTOR_INTERRUPT_CONTROLLER/ISR_ADR_2</twDest><twLogLvls>11</twLogLvls><twSrcSite>SLICE_X4Y53.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK_I_IBUFG_BUFG</twSrcClk><twPathDel><twSite>SLICE_X4Y53.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.447</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/IRQ_STATUS<7></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/IRQ_STATUS_5</twBEL></twPathDel><twPathDel><twSite>SLICE_X23Y50.A1</twSite><twDelType>net</twDelType><twFanCnt>19</twFanCnt><twDelInfo twEdge="twRising">2.401</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/IRQ_STATUS<5></twComp></twPathDel><twPathDel><twSite>SLICE_X23Y50.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SISR_ADR_9<23></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/Mmux_SCHN_ASN[0][4]_IRQ_STATUS[31]_Mux_11_o_91</twBEL></twPathDel><twPathDel><twSite>SLICE_X22Y51.D2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.606</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/Mmux_SCHN_ASN[0][4]_IRQ_STATUS[31]_Mux_11_o_91</twComp></twPathDel><twPathDel><twSite>SLICE_X22Y51.CMUX</twSite><twDelType>Topdc</twDelType><twDelInfo twEdge="twRising">0.338</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/Mmux_SCHN_ASN[0][4]_IRQ_STATUS[31]_Mux_11_o_7</twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/Mmux_SCHN_ASN[0][4]_IRQ_STATUS[31]_Mux_11_o_4</twBEL><twBEL>VECTOR_INTERRUPT_CONTROLLER/Mmux_SCHN_ASN[0][4]_IRQ_STATUS[31]_Mux_11_o_2_f7</twBEL></twPathDel><twPathDel><twSite>SLICE_X19Y56.B2</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">1.406</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][4]_IRQ_STATUS[31]_Mux_11_o</twComp></twPathDel><twPathDel><twSite>SLICE_X19Y56.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/D_CACHE_INST/PAGE_BASE_ADR_2<30></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[2][5]_OR_475_o1_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X19Y56.A5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.191</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[2][5]_OR_475_o1</twComp></twPathDel><twPathDel><twSite>SLICE_X19Y56.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/D_CACHE_INST/PAGE_BASE_ADR_2<30></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[4][5]_OR_477_o1_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X17Y56.A5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[4][5]_OR_477_o1</twComp></twPathDel><twPathDel><twSite>SLICE_X17Y56.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN_7<5></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[6][5]_OR_479_o1_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X17Y56.B6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[6][5]_OR_479_o1</twComp></twPathDel><twPathDel><twSite>SLICE_X17Y56.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN_7<5></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[7][5]_OR_480_o1</twBEL></twPathDel><twPathDel><twSite>SLICE_X17Y53.B2</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.822</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[7][5]_OR_480_o</twComp></twPathDel><twPathDel><twSite>SLICE_X17Y53.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>N323</twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[9][5]_OR_482_o1</twBEL></twPathDel><twPathDel><twSite>SLICE_X11Y58.D4</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">1.532</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[9][5]_OR_482_o</twComp></twPathDel><twPathDel><twSite>SLICE_X11Y58.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SISR_ADR_7<11></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/mux35261131</twBEL></twPathDel><twPathDel><twSite>SLICE_X21Y45.A5</twSite><twDelType>net</twDelType><twFanCnt>33</twFanCnt><twDelInfo twEdge="twRising">2.315</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/mux3526113</twComp></twPathDel><twPathDel><twSite>SLICE_X21Y45.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/D_CACHE_INST/PAGE_BASE_ADR_5<10></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/mux37463</twBEL></twPathDel><twPathDel><twSite>SLICE_X22Y46.C3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.524</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/mux37462</twComp></twPathDel><twPathDel><twSite>SLICE_X22Y46.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.205</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SISR_ADR_11<3></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/mux37467</twBEL></twPathDel><twPathDel><twSite>SLICE_X21Y44.A4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.643</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/mux37466</twComp></twPathDel><twPathDel><twSite>SLICE_X21Y44.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.322</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/ISR_ADR<3></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/mux37468</twBEL><twBEL>VECTOR_INTERRUPT_CONTROLLER/ISR_ADR_2</twBEL></twPathDel><twLogDel>3.384</twLogDel><twRouteDel>10.931</twRouteDel><twTotDel>14.315</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">CLK_I_IBUFG_BUFG</twDestClk><twPctLog>23.6</twPctLog><twPctRoute>76.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="14"><twConstPath anchorID="15" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>5.567</twSlack><twSrc BELType="FF">VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN_2_0</twSrc><twDest BELType="FF">VECTOR_INTERRUPT_CONTROLLER/ISR_ADR_2</twDest><twTotPathDel>14.333</twTotPathDel><twClkSkew dest = "0.522" src = "0.587">0.065</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN_2_0</twSrc><twDest BELType='FF'>VECTOR_INTERRUPT_CONTROLLER/ISR_ADR_2</twDest><twLogLvls>11</twLogLvls><twSrcSite>SLICE_X16Y56.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK_I_IBUFG_BUFG</twSrcClk><twPathDel><twSite>SLICE_X16Y56.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.447</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN_2<3></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN_2_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X6Y49.C2</twSite><twDelType>net</twDelType><twFanCnt>9</twFanCnt><twDelInfo twEdge="twRising">2.131</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN_2<0></twComp></twPathDel><twPathDel><twSite>SLICE_X6Y49.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.205</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/IRQ_STATUS_6_1</twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/Mmux_SCHN_ASN[2][4]_IRQ_STATUS[31]_Mux_15_o_91</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y52.D3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.428</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/Mmux_SCHN_ASN[2][4]_IRQ_STATUS[31]_Mux_15_o_91</twComp></twPathDel><twPathDel><twSite>SLICE_X14Y52.CMUX</twSite><twDelType>Topdc</twDelType><twDelInfo twEdge="twRising">0.338</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/Mmux_SCHN_ASN[2][4]_IRQ_STATUS[31]_Mux_15_o_9</twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/Mmux_SCHN_ASN[2][4]_IRQ_STATUS[31]_Mux_15_o_4</twBEL><twBEL>VECTOR_INTERRUPT_CONTROLLER/Mmux_SCHN_ASN[2][4]_IRQ_STATUS[31]_Mux_15_o_2_f7</twBEL></twPathDel><twPathDel><twSite>SLICE_X19Y56.B1</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.926</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[2][4]_IRQ_STATUS[31]_Mux_15_o</twComp></twPathDel><twPathDel><twSite>SLICE_X19Y56.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/D_CACHE_INST/PAGE_BASE_ADR_2<30></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[2][5]_OR_475_o1_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X19Y56.A5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.191</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[2][5]_OR_475_o1</twComp></twPathDel><twPathDel><twSite>SLICE_X19Y56.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/D_CACHE_INST/PAGE_BASE_ADR_2<30></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[4][5]_OR_477_o1_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X17Y56.A5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[4][5]_OR_477_o1</twComp></twPathDel><twPathDel><twSite>SLICE_X17Y56.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN_7<5></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[6][5]_OR_479_o1_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X17Y56.B6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[6][5]_OR_479_o1</twComp></twPathDel><twPathDel><twSite>SLICE_X17Y56.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN_7<5></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[7][5]_OR_480_o1</twBEL></twPathDel><twPathDel><twSite>SLICE_X17Y53.B2</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.822</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[7][5]_OR_480_o</twComp></twPathDel><twPathDel><twSite>SLICE_X17Y53.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>N323</twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[9][5]_OR_482_o1</twBEL></twPathDel><twPathDel><twSite>SLICE_X11Y58.D4</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">1.532</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[9][5]_OR_482_o</twComp></twPathDel><twPathDel><twSite>SLICE_X11Y58.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SISR_ADR_7<11></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/mux35261131</twBEL></twPathDel><twPathDel><twSite>SLICE_X21Y45.A5</twSite><twDelType>net</twDelType><twFanCnt>33</twFanCnt><twDelInfo twEdge="twRising">2.315</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/mux3526113</twComp></twPathDel><twPathDel><twSite>SLICE_X21Y45.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/D_CACHE_INST/PAGE_BASE_ADR_5<10></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/mux37463</twBEL></twPathDel><twPathDel><twSite>SLICE_X22Y46.C3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.524</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/mux37462</twComp></twPathDel><twPathDel><twSite>SLICE_X22Y46.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.205</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SISR_ADR_11<3></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/mux37467</twBEL></twPathDel><twPathDel><twSite>SLICE_X21Y44.A4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.643</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/mux37466</twComp></twPathDel><twPathDel><twSite>SLICE_X21Y44.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.322</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/ISR_ADR<3></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/mux37468</twBEL><twBEL>VECTOR_INTERRUPT_CONTROLLER/ISR_ADR_2</twBEL></twPathDel><twLogDel>3.330</twLogDel><twRouteDel>11.003</twRouteDel><twTotDel>14.333</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">CLK_I_IBUFG_BUFG</twDestClk><twPctLog>23.2</twPctLog><twPctRoute>76.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="16"><twConstPath anchorID="17" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>5.647</twSlack><twSrc BELType="FF">VECTOR_INTERRUPT_CONTROLLER/IRQ_STATUS_7</twSrc><twDest BELType="FF">VECTOR_INTERRUPT_CONTROLLER/ISR_ADR_2</twDest><twTotPathDel>14.210</twTotPathDel><twClkSkew dest = "0.522" src = "0.630">0.108</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>VECTOR_INTERRUPT_CONTROLLER/IRQ_STATUS_7</twSrc><twDest BELType='FF'>VECTOR_INTERRUPT_CONTROLLER/ISR_ADR_2</twDest><twLogLvls>11</twLogLvls><twSrcSite>SLICE_X4Y53.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK_I_IBUFG_BUFG</twSrcClk><twPathDel><twSite>SLICE_X4Y53.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.447</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/IRQ_STATUS<7></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/IRQ_STATUS_7</twBEL></twPathDel><twPathDel><twSite>SLICE_X23Y50.A3</twSite><twDelType>net</twDelType><twFanCnt>19</twFanCnt><twDelInfo twEdge="twRising">2.296</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/IRQ_STATUS<7></twComp></twPathDel><twPathDel><twSite>SLICE_X23Y50.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SISR_ADR_9<23></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/Mmux_SCHN_ASN[0][4]_IRQ_STATUS[31]_Mux_11_o_91</twBEL></twPathDel><twPathDel><twSite>SLICE_X22Y51.D2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.606</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/Mmux_SCHN_ASN[0][4]_IRQ_STATUS[31]_Mux_11_o_91</twComp></twPathDel><twPathDel><twSite>SLICE_X22Y51.CMUX</twSite><twDelType>Topdc</twDelType><twDelInfo twEdge="twRising">0.338</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/Mmux_SCHN_ASN[0][4]_IRQ_STATUS[31]_Mux_11_o_7</twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/Mmux_SCHN_ASN[0][4]_IRQ_STATUS[31]_Mux_11_o_4</twBEL><twBEL>VECTOR_INTERRUPT_CONTROLLER/Mmux_SCHN_ASN[0][4]_IRQ_STATUS[31]_Mux_11_o_2_f7</twBEL></twPathDel><twPathDel><twSite>SLICE_X19Y56.B2</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">1.406</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][4]_IRQ_STATUS[31]_Mux_11_o</twComp></twPathDel><twPathDel><twSite>SLICE_X19Y56.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/D_CACHE_INST/PAGE_BASE_ADR_2<30></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[2][5]_OR_475_o1_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X19Y56.A5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.191</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[2][5]_OR_475_o1</twComp></twPathDel><twPathDel><twSite>SLICE_X19Y56.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/D_CACHE_INST/PAGE_BASE_ADR_2<30></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[4][5]_OR_477_o1_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X17Y56.A5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[4][5]_OR_477_o1</twComp></twPathDel><twPathDel><twSite>SLICE_X17Y56.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN_7<5></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[6][5]_OR_479_o1_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X17Y56.B6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[6][5]_OR_479_o1</twComp></twPathDel><twPathDel><twSite>SLICE_X17Y56.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN_7<5></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[7][5]_OR_480_o1</twBEL></twPathDel><twPathDel><twSite>SLICE_X17Y53.B2</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.822</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[7][5]_OR_480_o</twComp></twPathDel><twPathDel><twSite>SLICE_X17Y53.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>N323</twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[9][5]_OR_482_o1</twBEL></twPathDel><twPathDel><twSite>SLICE_X11Y58.D4</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">1.532</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SCHN_ASN[0][5]_SCHN_ASN[9][5]_OR_482_o</twComp></twPathDel><twPathDel><twSite>SLICE_X11Y58.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SISR_ADR_7<11></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/mux35261131</twBEL></twPathDel><twPathDel><twSite>SLICE_X21Y45.A5</twSite><twDelType>net</twDelType><twFanCnt>33</twFanCnt><twDelInfo twEdge="twRising">2.315</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/mux3526113</twComp></twPathDel><twPathDel><twSite>SLICE_X21Y45.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/D_CACHE_INST/PAGE_BASE_ADR_5<10></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/mux37463</twBEL></twPathDel><twPathDel><twSite>SLICE_X22Y46.C3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.524</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/mux37462</twComp></twPathDel><twPathDel><twSite>SLICE_X22Y46.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.205</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SISR_ADR_11<3></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/mux37467</twBEL></twPathDel><twPathDel><twSite>SLICE_X21Y44.A4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.643</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/mux37466</twComp></twPathDel><twPathDel><twSite>SLICE_X21Y44.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.322</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/ISR_ADR<3></twComp><twBEL>VECTOR_INTERRUPT_CONTROLLER/mux37468</twBEL><twBEL>VECTOR_INTERRUPT_CONTROLLER/ISR_ADR_2</twBEL></twPathDel><twLogDel>3.384</twLogDel><twRouteDel>10.826</twRouteDel><twTotDel>14.210</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">CLK_I_IBUFG_BUFG</twDestClk><twPctLog>23.8</twPctLog><twPctRoute>76.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="603" iCriticalPaths="0" sType="EndPoint">Paths for end point STORM_TOP_INST/PROCESSOR_CORE/Multishifter/Multiplicator/Mmult_TEMP1 (DSP48_X0Y6.A2), 603 paths
</twPathRptBanner><twPathRpt anchorID="18"><twConstPath anchorID="19" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>5.564</twSlack><twSrc BELType="FF">STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR_0</twSrc><twDest BELType="DSP">STORM_TOP_INST/PROCESSOR_CORE/Multishifter/Multiplicator/Mmult_TEMP1</twDest><twTotPathDel>14.357</twTotPathDel><twClkSkew dest = "0.546" src = "0.590">0.044</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR_0</twSrc><twDest BELType='DSP'>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/Multiplicator/Mmult_TEMP1</twDest><twLogLvls>7</twLogLvls><twSrcSite>SLICE_X19Y6.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK_I_IBUFG_BUFG</twSrcClk><twPathDel><twSite>SLICE_X19Y6.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.391</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR<1></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X5Y13.B2</twSite><twDelType>net</twDelType><twFanCnt>71</twFanCnt><twDelInfo twEdge="twRising">3.000</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR<0></twComp></twPathDel><twPathDel><twSite>SLICE_X5Y13.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/read_access_port_c/ADR_O<4>11</twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mmux_MODE_INT11</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y20.C5</twSite><twDelType>net</twDelType><twFanCnt>14</twFanCnt><twDelInfo twEdge="twRising">1.080</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/MODE_INT<0></twComp></twPathDel><twPathDel><twSite>SLICE_X4Y20.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.204</twDelInfo><twComp>STORM_TOP_INST/I_CACHE_INST/PAGE_BASE_ADR_5<17></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Register_File/read_access_port_b/ADR_O<1>11</twBEL></twPathDel><twPathDel><twSite>SLICE_X5Y17.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.649</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/read_access_port_b/ADR_O<1>1</twComp></twPathDel><twPathDel><twSite>SLICE_X5Y17.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/I_CACHE_INST/PAGE_BASE_ADR_4<18></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Register_File/read_access_port_b/ADR_O<1>14</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y47.A2</twSite><twDelType>net</twDelType><twFanCnt>17</twFanCnt><twDelInfo twEdge="twRising">4.031</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/R_ADR_PORT_B<1></twComp></twPathDel><twPathDel><twSite>SLICE_X12Y47.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.203</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/R_ADR_PORT_B[4]_read_port_6_OUT<23></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE14_RAMA_D1</twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y37.C4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.314</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/R_ADR_PORT_B[4]_read_port_6_OUT<19></twComp></twPathDel><twPathDel><twSite>SLICE_X7Y37.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SISR_ADR_7<19></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O111</twBEL></twPathDel><twPathDel><twSite>SLICE_X11Y26.B4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.273</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O11</twComp></twPathDel><twPathDel><twSite>SLICE_X11Y26.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/OP_B_REG<20></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O112</twBEL></twPathDel><twPathDel><twSite>SLICE_X11Y26.A5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.187</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O111</twComp></twPathDel><twPathDel><twSite>SLICE_X11Y26.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/OP_B_REG<20></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O113</twBEL></twPathDel><twPathDel><twSite>DSP48_X0Y6.A2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.581</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/OF_OP_B_OUT<19></twComp></twPathDel><twPathDel><twSite>DSP48_X0Y6.CLK</twSite><twDelType>Tdspdck_A_A1REG</twDelType><twDelInfo twEdge="twRising">0.149</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/Multiplicator/Mmult_TEMP1</twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/Multiplicator/Mmult_TEMP1</twBEL></twPathDel><twLogDel>2.242</twLogDel><twRouteDel>12.115</twRouteDel><twTotDel>14.357</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">CLK_I_IBUFG_BUFG</twDestClk><twPctLog>15.6</twPctLog><twPctRoute>84.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="20"><twConstPath anchorID="21" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>6.061</twSlack><twSrc BELType="FF">STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR_0</twSrc><twDest BELType="DSP">STORM_TOP_INST/PROCESSOR_CORE/Multishifter/Multiplicator/Mmult_TEMP1</twDest><twTotPathDel>13.860</twTotPathDel><twClkSkew dest = "0.546" src = "0.590">0.044</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR_0</twSrc><twDest BELType='DSP'>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/Multiplicator/Mmult_TEMP1</twDest><twLogLvls>7</twLogLvls><twSrcSite>SLICE_X19Y6.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK_I_IBUFG_BUFG</twSrcClk><twPathDel><twSite>SLICE_X19Y6.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.391</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR<1></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X5Y13.B2</twSite><twDelType>net</twDelType><twFanCnt>71</twFanCnt><twDelInfo twEdge="twRising">3.000</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR<0></twComp></twPathDel><twPathDel><twSite>SLICE_X5Y13.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/read_access_port_c/ADR_O<4>11</twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mmux_MODE_INT11</twBEL></twPathDel><twPathDel><twSite>SLICE_X2Y18.B3</twSite><twDelType>net</twDelType><twFanCnt>14</twFanCnt><twDelInfo twEdge="twRising">1.542</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/MODE_INT<0></twComp></twPathDel><twPathDel><twSite>SLICE_X2Y18.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.205</twDelInfo><twComp>STORM_TOP_INST/I_CACHE_INST/PAGE_BASE_ADR_4<30></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Register_File/read_access_port_b/ADR_O<4>11</twBEL></twPathDel><twPathDel><twSite>SLICE_X2Y18.D1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.443</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/read_access_port_b/ADR_O<4>1</twComp></twPathDel><twPathDel><twSite>SLICE_X2Y18.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.205</twDelInfo><twComp>STORM_TOP_INST/I_CACHE_INST/PAGE_BASE_ADR_4<30></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Register_File/read_access_port_b/ADR_O<4>13</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y47.A5</twSite><twDelType>net</twDelType><twFanCnt>17</twFanCnt><twDelInfo twEdge="twRising">3.331</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/R_ADR_PORT_B<4></twComp></twPathDel><twPathDel><twSite>SLICE_X12Y47.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.203</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/R_ADR_PORT_B[4]_read_port_6_OUT<23></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE14_RAMA_D1</twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y37.C4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.314</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/R_ADR_PORT_B[4]_read_port_6_OUT<19></twComp></twPathDel><twPathDel><twSite>SLICE_X7Y37.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SISR_ADR_7<19></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O111</twBEL></twPathDel><twPathDel><twSite>SLICE_X11Y26.B4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.273</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O11</twComp></twPathDel><twPathDel><twSite>SLICE_X11Y26.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/OP_B_REG<20></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O112</twBEL></twPathDel><twPathDel><twSite>SLICE_X11Y26.A5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.187</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O111</twComp></twPathDel><twPathDel><twSite>SLICE_X11Y26.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/OP_B_REG<20></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O113</twBEL></twPathDel><twPathDel><twSite>DSP48_X0Y6.A2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.581</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/OF_OP_B_OUT<19></twComp></twPathDel><twPathDel><twSite>DSP48_X0Y6.CLK</twSite><twDelType>Tdspdck_A_A1REG</twDelType><twDelInfo twEdge="twRising">0.149</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/Multiplicator/Mmult_TEMP1</twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/Multiplicator/Mmult_TEMP1</twBEL></twPathDel><twLogDel>2.189</twLogDel><twRouteDel>11.671</twRouteDel><twTotDel>13.860</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">CLK_I_IBUFG_BUFG</twDestClk><twPctLog>15.8</twPctLog><twPctRoute>84.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="22"><twConstPath anchorID="23" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>6.379</twSlack><twSrc BELType="FF">STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR_0</twSrc><twDest BELType="DSP">STORM_TOP_INST/PROCESSOR_CORE/Multishifter/Multiplicator/Mmult_TEMP1</twDest><twTotPathDel>13.542</twTotPathDel><twClkSkew dest = "0.546" src = "0.590">0.044</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR_0</twSrc><twDest BELType='DSP'>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/Multiplicator/Mmult_TEMP1</twDest><twLogLvls>7</twLogLvls><twSrcSite>SLICE_X19Y6.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK_I_IBUFG_BUFG</twSrcClk><twPathDel><twSite>SLICE_X19Y6.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.391</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR<1></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y14.B2</twSite><twDelType>net</twDelType><twFanCnt>71</twFanCnt><twDelInfo twEdge="twRising">2.207</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/MCR_CMSR<0></twComp></twPathDel><twPathDel><twSite>SLICE_X4Y14.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.203</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Operation_Flow_Control/INS_BUF_SEL</twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Register_File/read_access_port_b/ADR_O<0>21</twBEL></twPathDel><twPathDel><twSite>SLICE_X6Y20.D3</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.872</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/read_access_port_b/ADR_O<0>_bdd5</twComp></twPathDel><twPathDel><twSite>SLICE_X6Y20.DMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.251</twDelInfo><twComp>STORM_TOP_INST/I_CACHE_INST/ADR_BUF<5></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Register_File/read_access_port_b/ADR_O<1>13</twBEL></twPathDel><twPathDel><twSite>SLICE_X5Y17.B6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.844</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/read_access_port_b/ADR_O<1>12</twComp></twPathDel><twPathDel><twSite>SLICE_X5Y17.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/I_CACHE_INST/PAGE_BASE_ADR_4<18></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Register_File/read_access_port_b/ADR_O<1>14</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y47.A2</twSite><twDelType>net</twDelType><twFanCnt>17</twFanCnt><twDelInfo twEdge="twRising">4.031</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/R_ADR_PORT_B<1></twComp></twPathDel><twPathDel><twSite>SLICE_X12Y47.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.203</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/R_ADR_PORT_B[4]_read_port_6_OUT<23></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE14_RAMA_D1</twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y37.C4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.314</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Register_File/R_ADR_PORT_B[4]_read_port_6_OUT<19></twComp></twPathDel><twPathDel><twSite>SLICE_X7Y37.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>VECTOR_INTERRUPT_CONTROLLER/SISR_ADR_7<19></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O111</twBEL></twPathDel><twPathDel><twSite>SLICE_X11Y26.B4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.273</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O11</twComp></twPathDel><twPathDel><twSite>SLICE_X11Y26.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/OP_B_REG<20></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O112</twBEL></twPathDel><twPathDel><twSite>SLICE_X11Y26.A5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.187</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O111</twComp></twPathDel><twPathDel><twSite>SLICE_X11Y26.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/OP_B_REG<20></twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Operand_Fetch_Unit/Mmux_OP_B_O113</twBEL></twPathDel><twPathDel><twSite>DSP48_X0Y6.A2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.581</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/OF_OP_B_OUT<19></twComp></twPathDel><twPathDel><twSite>DSP48_X0Y6.CLK</twSite><twDelType>Tdspdck_A_A1REG</twDelType><twDelInfo twEdge="twRising">0.149</twDelInfo><twComp>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/Multiplicator/Mmult_TEMP1</twComp><twBEL>STORM_TOP_INST/PROCESSOR_CORE/Multishifter/Multiplicator/Mmult_TEMP1</twBEL></twPathDel><twLogDel>2.233</twLogDel><twRouteDel>11.309</twRouteDel><twTotDel>13.542</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">CLK_I_IBUFG_BUFG</twDestClk><twPctLog>16.5</twPctLog><twPctRoute>83.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: NET "CLK_I_IBUFG" PERIOD = 20 ns HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point INTERNAL_SRAM_MEMORY/Mram_MEM_FILE2 (RAMB16_X1Y16.ADDRA10), 1 path
</twPathRptBanner><twPathRpt anchorID="24"><twConstPath anchorID="25" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.340</twSlack><twSrc BELType="FF">STORM_TOP_INST/BUS_UNIT_INST/WB_ADR_O_11</twSrc><twDest BELType="RAM">INTERNAL_SRAM_MEMORY/Mram_MEM_FILE2</twDest><twTotPathDel>0.342</twTotPathDel><twClkSkew dest = "0.077" src = "0.075">-0.002</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="20" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>STORM_TOP_INST/BUS_UNIT_INST/WB_ADR_O_11</twSrc><twDest BELType='RAM'>INTERNAL_SRAM_MEMORY/Mram_MEM_FILE2</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X16Y33.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="20.000">CLK_I_IBUFG_BUFG</twSrcClk><twPathDel><twSite>SLICE_X16Y33.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.234</twDelInfo><twComp>STORM_TOP_INST/BUS_UNIT_INST/WB_ADR_O<11></twComp><twBEL>STORM_TOP_INST/BUS_UNIT_INST/WB_ADR_O_11</twBEL></twPathDel><twPathDel><twSite>RAMB16_X1Y16.ADDRA10</twSite><twDelType>net</twDelType><twFanCnt>30</twFanCnt><twDelInfo twEdge="twFalling">0.174</twDelInfo><twComp>STORM_TOP_INST/BUS_UNIT_INST/WB_ADR_O<11></twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>RAMB16_X1Y16.CLKA</twSite><twDelType>Trckc_ADDRA</twDelType><twDelInfo twEdge="twFalling">-0.066</twDelInfo><twComp>INTERNAL_SRAM_MEMORY/Mram_MEM_FILE2</twComp><twBEL>INTERNAL_SRAM_MEMORY/Mram_MEM_FILE2</twBEL></twPathDel><twLogDel>0.168</twLogDel><twRouteDel>0.174</twRouteDel><twTotDel>0.342</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">CLK_I_IBUFG_BUFG</twDestClk><twPctLog>49.1</twPctLog><twPctRoute>50.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point SDRAM/ctrl/Mshreg_data_ready_delay_0 (SLICE_X12Y30.AI), 1 path
</twPathRptBanner><twPathRpt anchorID="26"><twConstPath anchorID="27" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.382</twSlack><twSrc BELType="FF">SDRAM/ctrl/data_ready_delay_4</twSrc><twDest BELType="FF">SDRAM/ctrl/Mshreg_data_ready_delay_0</twDest><twTotPathDel>0.382</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>SDRAM/ctrl/data_ready_delay_4</twSrc><twDest BELType='FF'>SDRAM/ctrl/Mshreg_data_ready_delay_0</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X12Y30.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="20.000">CLK_I_IBUFG_BUFG</twSrcClk><twPathDel><twSite>SLICE_X12Y30.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.234</twDelInfo><twComp>SDRAM/ctrl/data_ready_delay<4></twComp><twBEL>SDRAM/ctrl/data_ready_delay_4</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y30.AI</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.118</twDelInfo><twComp>SDRAM/ctrl/data_ready_delay<4></twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X12Y30.CLK</twSite><twDelType>Tdh</twDelType><twDelInfo twEdge="twFalling">0.030</twDelInfo><twComp>SDRAM/ctrl/data_ready_delay<4></twComp><twBEL>SDRAM/ctrl/Mshreg_data_ready_delay_0</twBEL></twPathDel><twLogDel>0.264</twLogDel><twRouteDel>0.118</twRouteDel><twTotDel>0.382</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">CLK_I_IBUFG_BUFG</twDestClk><twPctLog>69.1</twPctLog><twPctRoute>30.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point GP_UART_0/Uart_RxUnit/DataO_4 (SLICE_X15Y17.AX), 1 path
</twPathRptBanner><twPathRpt anchorID="28"><twConstPath anchorID="29" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.392</twSlack><twSrc BELType="FF">GP_UART_0/Uart_RxUnit/RReg_4</twSrc><twDest BELType="FF">GP_UART_0/Uart_RxUnit/DataO_4</twDest><twTotPathDel>0.394</twTotPathDel><twClkSkew dest = "0.045" src = "0.043">-0.002</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>GP_UART_0/Uart_RxUnit/RReg_4</twSrc><twDest BELType='FF'>GP_UART_0/Uart_RxUnit/DataO_4</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X14Y17.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="20.000">CLK_I_IBUFG_BUFG</twSrcClk><twPathDel><twSite>SLICE_X14Y17.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>GP_UART_0/Uart_RxUnit/RReg<7></twComp><twBEL>GP_UART_0/Uart_RxUnit/RReg_4</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y17.AX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.135</twDelInfo><twComp>GP_UART_0/Uart_RxUnit/RReg<4></twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X15Y17.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.059</twDelInfo><twComp>GP_UART_0/Uart_RxUnit/DataO<7></twComp><twBEL>GP_UART_0/Uart_RxUnit/DataO_4</twBEL></twPathDel><twLogDel>0.259</twLogDel><twRouteDel>0.135</twRouteDel><twTotDel>0.394</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">CLK_I_IBUFG_BUFG</twDestClk><twPctLog>65.7</twPctLog><twPctRoute>34.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="30"><twPinLimitBanner>Component Switching Limit Checks: NET "CLK_I_IBUFG" PERIOD = 20 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="31" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="16.876" period="20.000" constraintValue="20.000" deviceLimit="3.124" freqLimit="320.102" physResource="INTERNAL_SRAM_MEMORY/Mram_MEM_FILE1/CLKA" logResource="INTERNAL_SRAM_MEMORY/Mram_MEM_FILE1/CLKA" locationPin="RAMB16_X0Y2.CLKA" clockNet="CLK_I_IBUFG_BUFG"/><twPinLimit anchorID="32" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="16.876" period="20.000" constraintValue="20.000" deviceLimit="3.124" freqLimit="320.102" physResource="INTERNAL_SRAM_MEMORY/Mram_MEM_FILE2/CLKA" logResource="INTERNAL_SRAM_MEMORY/Mram_MEM_FILE2/CLKA" locationPin="RAMB16_X1Y16.CLKA" clockNet="CLK_I_IBUFG_BUFG"/><twPinLimit anchorID="33" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="16.876" period="20.000" constraintValue="20.000" deviceLimit="3.124" freqLimit="320.102" physResource="INTERNAL_SRAM_MEMORY/Mram_MEM_FILE3/CLKA" logResource="INTERNAL_SRAM_MEMORY/Mram_MEM_FILE3/CLKA" locationPin="RAMB16_X0Y4.CLKA" clockNet="CLK_I_IBUFG_BUFG"/></twPinLimitRpt></twConst><twUnmetConstCnt anchorID="34">0</twUnmetConstCnt><twDataSheet anchorID="35" twNameLen="15"><twClk2SUList anchorID="36" twDestWidth="5"><twDest>CLK_I</twDest><twClk2SU><twSrc>CLK_I</twSrc><twRiseRise>14.486</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum anchorID="37"><twErrCnt>0</twErrCnt><twScore>0</twScore><twSetupScore>0</twSetupScore><twHoldScore>0</twHoldScore><twConstCov><twPathCnt>1647215</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>31970</twConnCnt></twConstCov><twStats anchorID="38"><twMinPer>14.486</twMinPer><twFootnote number="1" /><twMaxFreq>69.032</twMaxFreq></twStats></twSum><twFoot><twFootnoteExplanation number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>Mon Feb 23 20:02:27 2015 </twTimestamp></twFoot><twClientInfo anchorID="39"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
Peak Memory Usage: 489 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>