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fix(risc_v_simulator): replace println with log #728

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fix(risc_v_simulator): replace println with log

fix(risc_v_simulator): replace println with log #728

Run time

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Job Run time
tests
3m 36s
cargo fmt
28s
build_cli_no_verifiers
11m 1s
circuits_generated
3m 25s
ISA tests for simulator
2m 17s
build_cli_with_verify
2m 54s
risc_v_tests_delegations
3m 25s
build_cli_no_verifiers_512
3m 42s
full_recursion_fast
2m 47s
build_verifier
4m 4s
basic_example
2m 49s
large_example
6m 0s
delegation_example
5m 17s
full_recursion
3m 42s
oh_bender_incremental_proofs
1m 37s
verification_example
7m 32s
1h 4m 36s