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<title>Deliverable Validation — FPGA Algotrading System</title>
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<div class="wrap">
<div class="masthead">
<div>
<p class="eyebrow">Validation Report</p>
<h1>FPGA Algorithmic Trading System · Nasdaq Equities</h1>
</div>
<div class="meta">
generated by scripts/validate.py<br>
243 files · 109,740 lines · 27 tiers
</div>
</div>
<div class="verdict is-fail"><span class="lamp"></span><span class="txt"><b>42 blocking findings and 0 unmet requirements.</b> Work is still landing — sections below show exactly which artifacts are outstanding and which references do not yet resolve.</span></div>
<div class="readouts">
<div class="ro"><div class="k">Deliverables</div><div class="v">243<span class="u">files</span></div></div>
<div class="ro"><div class="k">Written</div><div class="v">109,740<span class="u">lines</span></div></div>
<div class="ro"><div class="k">RTL modules</div><div class="v">55</div></div>
<div class="ro warn"><div class="k">Reqs met</div><div class="v">95.8<span class="u">%</span></div></div>
<div class="ro fail"><div class="k">Blocking</div><div class="v">42</div></div>
<div class="ro warn"><div class="k">Advisory</div><div class="v">73</div></div>
</div>
<section>
<div class="shead">
<h2>Requirements traceability</h2>
<span class="chip pass">23 met</span> <span class="chip warn">1 partial</span> <span class="chip fail">0 missing</span>
<span class="desc">every stated request → the artifacts that satisfy it</span>
</div>
<p class="lede">Each row is something that was asked for, resolved against files that
actually exist on disk. <b>Found / required</b> is a file count, not a quality judgement —
a met row means the artifacts are present, not that they are correct.</p>
<div class="scroll"><table>
<thead><tr><th>Requirement</th><th style="text-align:right">Found</th><th>Progress</th><th>Status</th><th>Example artifacts</th></tr></thead>
<tbody><tr><td>Create a CLAUDE.md file</td><td class="n">1<span style="color:var(--muted)">/1</span></td><td style="width:110px"><span class="meter pass"><i style="width:100%"></i></span></td><td><span class="chip pass">met</span></td><td class="dim mono">CLAUDE.md</td></tr><tr><td>Create a manuals folder</td><td class="n">1<span style="color:var(--muted)">/1</span></td><td style="width:110px"><span class="meter pass"><i style="width:100%"></i></span></td><td><span class="chip pass">met</span></td><td class="dim mono">manuals/README.md</td></tr><tr><td>Manuals cover main FPGA concepts, hierarchically</td><td class="n">15<span style="color:var(--muted)">/12</span></td><td style="width:110px"><span class="meter pass"><i style="width:100%"></i></span></td><td><span class="chip pass">met</span></td><td class="dim mono">manuals/00-foundations/01-digital-logic-and-timing.md, manuals/00-foundations/02-fpga-architecture.md</td></tr><tr><td>Manuals cover main Algotrading concepts, hierarchically</td><td class="n">12<span style="color:var(--muted)">/10</span></td><td style="width:110px"><span class="meter pass"><i style="width:100%"></i></span></td><td><span class="chip pass">met</span></td><td class="dim mono">manuals/03-algotrading/01-market-microstructure.md, manuals/03-algotrading/02-order-types-and-matching-engines.md</td></tr><tr><td>Optimization guidance for the trading system</td><td class="n">5<span style="color:var(--muted)">/5</span></td><td style="width:110px"><span class="meter pass"><i style="width:100%"></i></span></td><td><span class="chip pass">met</span></td><td class="dim mono">manuals/05-optimization/01-latency-budgeting.md, manuals/05-optimization/02-fmax-and-timing-optimization.md</td></tr><tr><td>Operations and reference tiers</td><td class="n">8<span style="color:var(--muted)">/6</span></td><td style="width:110px"><span class="meter pass"><i style="width:100%"></i></span></td><td><span class="chip pass">met</span></td><td class="dim mono">manuals/06-operations/01-build-and-release.md, manuals/06-operations/02-deployment-and-colocation.md</td></tr><tr><td>Task list for full FPGA-driven algotrading</td><td class="n">1<span style="color:var(--muted)">/1</span></td><td style="width:110px"><span class="meter pass"><i style="width:100%"></i></span></td><td><span class="chip pass">met</span></td><td class="dim mono">TASKS.md</td></tr><tr><td>Detailed manuals on Nasdaq algotrading rules</td><td class="n">9<span style="color:var(--muted)">/9</span></td><td style="width:110px"><span class="meter pass"><i style="width:100%"></i></span></td><td><span class="chip pass">met</span></td><td class="dim mono">manuals/08-nasdaq/01-market-structure.md, manuals/08-nasdaq/02-sessions-auctions-and-halts.md</td></tr><tr><td>FPGA top module code</td><td class="n">1<span style="color:var(--muted)">/1</span></td><td style="width:110px"><span class="meter pass"><i style="width:100%"></i></span></td><td><span class="chip pass">met</span></td><td class="dim mono">rtl/fpga_top.sv</td></tr><tr><td>Shared type/interface contract</td><td class="n">3<span style="color:var(--muted)">/2</span></td><td style="width:110px"><span class="meter pass"><i style="width:100%"></i></span></td><td><span class="chip pass">met</span></td><td class="dim mono">rtl/pkg/itch_pkg.sv, rtl/pkg/sat_arith_pkg.sv</td></tr><tr><td>Remaining RTL — common primitives</td><td class="n">13<span style="color:var(--muted)">/10</span></td><td style="width:110px"><span class="meter pass"><i style="width:100%"></i></span></td><td><span class="chip pass">met</span></td><td class="dim mono">rtl/common/async_fifo.sv, rtl/common/cdc_handshake.sv</td></tr><tr><td>Remaining RTL — Ethernet/MAC</td><td class="n">5<span style="color:var(--muted)">/4</span></td><td style="width:110px"><span class="meter pass"><i style="width:100%"></i></span></td><td><span class="chip pass">met</span></td><td class="dim mono">rtl/eth/crc32_eth.sv, rtl/eth/eth_10g_wrapper.sv</td></tr><tr><td>Remaining RTL — network RX</td><td class="n">5<span style="color:var(--muted)">/4</span></td><td style="width:110px"><span class="meter pass"><i style="width:100%"></i></span></td><td><span class="chip pass">met</span></td><td class="dim mono">rtl/net/ab_arbiter.sv, rtl/net/eth_ip_udp_rx.sv</td></tr><tr><td>Remaining RTL — feed handler</td><td class="n">4<span style="color:var(--muted)">/4</span></td><td style="width:110px"><span class="meter pass"><i style="width:100%"></i></span></td><td><span class="chip pass">met</span></td><td class="dim mono">rtl/feed/feed_handler.sv, rtl/feed/itch_decoder.sv</td></tr><tr><td>Remaining RTL — order book</td><td class="n">5<span style="color:var(--muted)">/4</span></td><td style="width:110px"><span class="meter pass"><i style="width:100%"></i></span></td><td><span class="chip pass">met</span></td><td class="dim mono">rtl/book/book_engine.sv, rtl/book/book_pkg.sv</td></tr><tr><td>Remaining RTL — strategy engine</td><td class="n">6<span style="color:var(--muted)">/5</span></td><td style="width:110px"><span class="meter pass"><i style="width:100%"></i></span></td><td><span class="chip pass">met</span></td><td class="dim mono">rtl/strategy/param_table.sv, rtl/strategy/position_track.sv</td></tr><tr><td>Remaining RTL — risk gate and kill switch</td><td class="n">6<span style="color:var(--muted)">/5</span></td><td style="width:110px"><span class="meter pass"><i style="width:100%"></i></span></td><td><span class="chip pass">met</span></td><td class="dim mono">rtl/risk/kill_switch.sv, rtl/risk/order_token_gen.sv</td></tr><tr><td>Remaining RTL — order gateway</td><td class="n">7<span style="color:var(--muted)">/6</span></td><td style="width:110px"><span class="meter pass"><i style="width:100%"></i></span></td><td><span class="chip pass">met</span></td><td class="dim mono">rtl/order/credit_mgr.sv, rtl/order/order_gateway.sv</td></tr><tr><td>Remaining RTL — control plane and telemetry</td><td class="n">7<span style="color:var(--muted)">/6</span></td><td style="width:110px"><span class="meter pass"><i style="width:100%"></i></span></td><td><span class="chip pass">met</span></td><td class="dim mono">rtl/ctrl/csr_regfile.sv, rtl/ctrl/dma_log_ring.sv</td></tr><tr><td>Constraints and build flow</td><td class="n">12<span style="color:var(--muted)">/8</span></td><td style="width:110px"><span class="meter pass"><i style="width:100%"></i></span></td><td><span class="chip pass">met</span></td><td class="dim mono">constraints/cdc.xdc, constraints/clocks.xdc</td></tr><tr><td>Verification scaffolding and testbenches</td><td class="n">15<span style="color:var(--muted)">/10</span></td><td style="width:110px"><span class="meter pass"><i style="width:100%"></i></span></td><td><span class="chip pass">met</span></td><td class="dim mono">tb/book/test_book_engine.py, tb/book/test_book_soak.py</td></tr><tr><td>Host slow-path software</td><td class="n">58<span style="color:var(--muted)">/5</span></td><td style="width:110px"><span class="meter pass"><i style="width:100%"></i></span></td><td><span class="chip pass">met</span></td><td class="dim mono">host/README.md, host/include/trading/ctrld/ctrl_error.hpp</td></tr><tr><td>Design decision records</td><td class="n">4<span style="color:var(--muted)">/5</span></td><td style="width:110px"><span class="meter warn"><i style="width:80%"></i></span></td><td><span class="chip warn">partial</span></td><td class="dim mono">docs/adr/0003-datapath-width-and-clock.md, docs/adr/0004-single-clock-domain.md</td></tr><tr><td>Deep-dive manual tier</td><td class="n">10<span style="color:var(--muted)">/10</span></td><td style="width:110px"><span class="meter pass"><i style="width:100%"></i></span></td><td><span class="chip pass">met</span></td><td class="dim mono">manuals/09-deep-dives/01-queue-position-and-fill-probability.md, manuals/09-deep-dives/02-adverse-selection-and-toxicity.md</td></tr></tbody>
</table></div>
</section>
<section>
<div class="shead">
<h2>Structural checks</h2>
<span class="desc">internal consistency of the tree</span>
</div>
<div class="gauges">
<div class="gauge pass">
<div class="k">Top-level contract</div>
<div class="v">100<span class="u">%</span></div>
<span class="meter pass"><i style="width:100%"></i></span>
<div class="note">11 of 11 modules
instantiated in <code>rtl/fpga_top.sv</code> have a matching file.<br>Every instantiated module has a file.</div>
</div>
<div class="gauge warn">
<div class="k">Cross-references</div>
<div class="v">42<span class="u">broken</span></div>
<span class="meter warn"><i style="width:97.91%"></i></span>
<div class="note">2,008 relative links checked across every markdown file.
A broken link usually means a manual was renamed after something linked to it.</div>
</div>
<div class="gauge warn">
<div class="k">Testbench coverage</div>
<div class="v">56.4<span class="u">%</span></div>
<span class="meter warn"><i style="width:56.4%"></i></span>
<div class="note">31 of 55 RTL modules are
referenced by a file under <code>tb/</code>.<br><code>async_fifo</code> <code>cdc_handshake</code> <code>cdc_pulse</code> <code>cdc_sync_bit</code> <code>clk_rst_gen</code> <code>counter_bank</code> <code>csr_regfile</code> <code>delay_line</code> <code>dma_log_ring</code> <code>eth_10g_wrapper</code> <code>fixed_arbiter</code> <code>fv_axis_props</code> <span style='color:var(--muted)'>+12 more</span></div>
</div>
</div>
</section>
<section>
<div class="shead">
<h2>Inventory</h2>
<span class="desc">what exists, by tier</span>
</div>
<div class="scroll"><table>
<thead><tr><th>Tier</th><th style="text-align:right">Files</th><th style="text-align:right">Lines</th><th>Relative volume</th></tr></thead>
<tbody><tr><td>Host software</td><td class="n">58</td><td class="n">20,347</td><td style="width:190px"><span class="meter"><i style="width:100%"></i></span></td></tr><tr><td>Root</td><td class="n">24</td><td class="n">13,942</td><td style="width:190px"><span class="meter"><i style="width:68.52%"></i></span></td></tr><tr><td>Verification</td><td class="n">18</td><td class="n">10,615</td><td style="width:190px"><span class="meter"><i style="width:52.17%"></i></span></td></tr><tr><td>Manuals · Deep Dives</td><td class="n">10</td><td class="n">5,983</td><td style="width:190px"><span class="meter"><i style="width:29.4%"></i></span></td></tr><tr><td>Manuals · Nasdaq</td><td class="n">9</td><td class="n">4,859</td><td style="width:190px"><span class="meter"><i style="width:23.88%"></i></span></td></tr><tr><td>RTL · Risk gate</td><td class="n">6</td><td class="n">4,167</td><td style="width:190px"><span class="meter"><i style="width:20.48%"></i></span></td></tr><tr><td>RTL · Order gateway</td><td class="n">7</td><td class="n">4,100</td><td style="width:190px"><span class="meter"><i style="width:20.15%"></i></span></td></tr><tr><td>RTL · Control plane</td><td class="n">5</td><td class="n">3,894</td><td style="width:190px"><span class="meter"><i style="width:19.14%"></i></span></td></tr><tr><td>Manuals · System Architecture</td><td class="n">6</td><td class="n">3,754</td><td style="width:190px"><span class="meter"><i style="width:18.45%"></i></span></td></tr><tr><td>RTL · Strategy engine</td><td class="n">7</td><td class="n">3,021</td><td style="width:190px"><span class="meter"><i style="width:14.85%"></i></span></td></tr><tr><td>RTL · Ethernet/MAC</td><td class="n">6</td><td class="n">2,989</td><td style="width:190px"><span class="meter"><i style="width:14.69%"></i></span></td></tr><tr><td>Build scripts</td><td class="n">7</td><td class="n">2,982</td><td style="width:190px"><span class="meter"><i style="width:14.66%"></i></span></td></tr><tr><td>Design docs</td><td class="n">5</td><td class="n">2,834</td><td style="width:190px"><span class="meter"><i style="width:13.93%"></i></span></td></tr><tr><td>RTL · Common primitives</td><td class="n">14</td><td class="n">2,808</td><td style="width:190px"><span class="meter"><i style="width:13.8%"></i></span></td></tr><tr><td>Manuals · Algotrading</td><td class="n">6</td><td class="n">2,751</td><td style="width:190px"><span class="meter"><i style="width:13.52%"></i></span></td></tr><tr><td>RTL · Network RX</td><td class="n">5</td><td class="n">2,541</td><td style="width:190px"><span class="meter"><i style="width:12.49%"></i></span></td></tr><tr><td>Manuals · FPGA Design</td><td class="n">6</td><td class="n">2,425</td><td style="width:190px"><span class="meter"><i style="width:11.92%"></i></span></td></tr><tr><td>RTL · Feed handler</td><td class="n">5</td><td class="n">2,274</td><td style="width:190px"><span class="meter"><i style="width:11.18%"></i></span></td></tr><tr><td>Manuals · Optimization</td><td class="n">5</td><td class="n">2,266</td><td style="width:190px"><span class="meter"><i style="width:11.14%"></i></span></td></tr><tr><td>Manuals · Reference</td><td class="n">4</td><td class="n">1,757</td><td style="width:190px"><span class="meter"><i style="width:8.635%"></i></span></td></tr><tr><td>Manuals · Operations</td><td class="n">4</td><td class="n">1,703</td><td style="width:190px"><span class="meter"><i style="width:8.37%"></i></span></td></tr><tr><td>Manuals · Networking</td><td class="n">4</td><td class="n">1,608</td><td style="width:190px"><span class="meter"><i style="width:7.903%"></i></span></td></tr><tr><td>RTL · Order book</td><td class="n">6</td><td class="n">1,580</td><td style="width:190px"><span class="meter"><i style="width:7.765%"></i></span></td></tr><tr><td>Manuals · Foundations</td><td class="n">5</td><td class="n">1,259</td><td style="width:190px"><span class="meter"><i style="width:6.188%"></i></span></td></tr><tr><td>Constraints</td><td class="n">5</td><td class="n">1,236</td><td style="width:190px"><span class="meter"><i style="width:6.075%"></i></span></td></tr><tr><td>RTL · Telemetry</td><td class="n">3</td><td class="n">1,160</td><td style="width:190px"><span class="meter"><i style="width:5.701%"></i></span></td></tr><tr><td>RTL · Packages</td><td class="n">3</td><td class="n">885</td><td style="width:190px"><span class="meter"><i style="width:4.35%"></i></span></td></tr></tbody>
</table></div>
</section>
<section>
<div class="shead">
<h2>Findings by class</h2>
<span class="desc">grouped, most frequent first</span>
</div>
<div class="scroll"><table>
<thead><tr><th>Class</th><th>Key</th><th style="text-align:right">Count</th></tr></thead>
<tbody><tr><td>Cross-reference integrity</td><td class="mono dim">broken-link</td><td class="n">42</td></tr><tr><td>RTL coding rules</td><td class="mono dim">rtl-discipline</td><td class="n">29</td></tr><tr><td>Testbench coverage</td><td class="mono dim">coverage</td><td class="n">24</td></tr><tr><td>Module header discipline</td><td class="mono dim">header</td><td class="n">20</td></tr></tbody>
</table></div>
</section>
<section>
<div class="shead">
<h2>Finding log</h2>
<span class="desc">most severe first</span>
</div>
<div class="scroll"><table>
<thead><tr><th style="width:76px">Severity</th><th>Class</th><th>Location</th><th>Detail</th></tr></thead>
<tbody><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">docs/adr/0003-datapath-width-and-clock.md</td><td>link target does not exist: ../latency-budget.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">docs/adr/0003-datapath-width-and-clock.md</td><td>link target does not exist: README.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">docs/adr/0003-datapath-width-and-clock.md</td><td>link target does not exist: ../latency-budget.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">docs/adr/0004-single-clock-domain.md</td><td>link target does not exist: README.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">docs/adr/0004-single-clock-domain.md</td><td>link target does not exist: ../latency-budget.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">docs/register-map.md</td><td>link target does not exist: latency-budget.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">docs/register-map.md</td><td>link target does not exist: adr/README.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">docs/resource-budget.md</td><td>link target does not exist: latency-budget.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">docs/resource-budget.md</td><td>link target does not exist: latency-budget.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">docs/resource-budget.md</td><td>link target does not exist: latency-budget.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">docs/resource-budget.md</td><td>link target does not exist: latency-budget.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">docs/resource-budget.md</td><td>link target does not exist: latency-budget.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">docs/resource-budget.md</td><td>link target does not exist: latency-budget.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">docs/resource-budget.md</td><td>link target does not exist: adr/README.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/10-quant-methods/01-signal-construction.md</td><td>link target does not exist: 05-parameter-calibration.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/10-quant-methods/01-signal-construction.md</td><td>link target does not exist: 05-parameter-calibration.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/10-quant-methods/01-signal-construction.md</td><td>link target does not exist: 03-statistical-foundations.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/10-quant-methods/01-signal-construction.md</td><td>link target does not exist: 05-parameter-calibration.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/10-quant-methods/01-signal-construction.md</td><td>link target does not exist: 04-backtesting-and-simulation.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/10-quant-methods/01-signal-construction.md</td><td>link target does not exist: 05-parameter-calibration.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/10-quant-methods/01-signal-construction.md</td><td>link target does not exist: README.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/10-quant-methods/01-signal-construction.md</td><td>link target does not exist: 03-statistical-foundations.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/10-quant-methods/01-signal-construction.md</td><td>link target does not exist: 04-backtesting-and-simulation.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/10-quant-methods/01-signal-construction.md</td><td>link target does not exist: 05-parameter-calibration.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/10-quant-methods/02-fair-value-and-pricing.md</td><td>link target does not exist: 05-parameter-calibration.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/10-quant-methods/02-fair-value-and-pricing.md</td><td>link target does not exist: 05-parameter-calibration.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/10-quant-methods/02-fair-value-and-pricing.md</td><td>link target does not exist: 03-statistical-foundations.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/10-quant-methods/02-fair-value-and-pricing.md</td><td>link target does not exist: README.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/10-quant-methods/02-fair-value-and-pricing.md</td><td>link target does not exist: 03-statistical-foundations.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/10-quant-methods/02-fair-value-and-pricing.md</td><td>link target does not exist: 04-backtesting-and-simulation.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/10-quant-methods/02-fair-value-and-pricing.md</td><td>link target does not exist: 05-parameter-calibration.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/11-platform/01-card-selection.md</td><td>link target does not exist: 04-thermals-and-power.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/11-platform/01-card-selection.md</td><td>link target does not exist: 04-thermals-and-power.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/11-platform/01-card-selection.md</td><td>link target does not exist: 03-bringup-procedure.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/11-platform/01-card-selection.md</td><td>link target does not exist: 03-bringup-procedure.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/11-platform/01-card-selection.md</td><td>link target does not exist: 04-thermals-and-power.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/11-platform/01-card-selection.md</td><td>link target does not exist: 03-bringup-procedure.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/11-platform/01-card-selection.md</td><td>link target does not exist: 03-bringup-procedure.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/11-platform/01-card-selection.md</td><td>link target does not exist: 04-thermals-and-power.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/11-platform/02-vendor-ecosystem.md</td><td>link target does not exist: 03-bringup-procedure.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/11-platform/02-vendor-ecosystem.md</td><td>link target does not exist: 03-bringup-procedure.md</td></tr><tr class="sev sev-error"><td><span class="chip fail">error</span></td><td class="mono dim">broken-link</td><td class="mono" style="font-size:12px">manuals/11-platform/02-vendor-ecosystem.md</td><td>link target does not exist: 03-bringup-procedure.md</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">coverage</td><td class="mono" style="font-size:12px">rtl/common/async_fifo.sv</td><td>no testbench references `async_fifo` — CLAUDE.md §4 requires a testbench for every fast-path module</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">coverage</td><td class="mono" style="font-size:12px">rtl/common/cdc_handshake.sv</td><td>no testbench references `cdc_handshake` — CLAUDE.md §4 requires a testbench for every fast-path module</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">coverage</td><td class="mono" style="font-size:12px">rtl/common/cdc_pulse.sv</td><td>no testbench references `cdc_pulse` — CLAUDE.md §4 requires a testbench for every fast-path module</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">coverage</td><td class="mono" style="font-size:12px">rtl/common/cdc_sync_bit.sv</td><td>no testbench references `cdc_sync_bit` — CLAUDE.md §4 requires a testbench for every fast-path module</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">coverage</td><td class="mono" style="font-size:12px">rtl/common/clk_rst_gen.sv</td><td>no testbench references `clk_rst_gen` — CLAUDE.md §4 requires a testbench for every fast-path module</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">coverage</td><td class="mono" style="font-size:12px">rtl/common/counter_bank.sv</td><td>no testbench references `counter_bank` — CLAUDE.md §4 requires a testbench for every fast-path module</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">coverage</td><td class="mono" style="font-size:12px">rtl/common/delay_line.sv</td><td>no testbench references `delay_line` — CLAUDE.md §4 requires a testbench for every fast-path module</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">coverage</td><td class="mono" style="font-size:12px">rtl/common/fixed_arbiter.sv</td><td>no testbench references `fixed_arbiter` — CLAUDE.md §4 requires a testbench for every fast-path module</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">coverage</td><td class="mono" style="font-size:12px">rtl/common/prio_encoder.sv</td><td>no testbench references `prio_encoder` — CLAUDE.md §4 requires a testbench for every fast-path module</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">coverage</td><td class="mono" style="font-size:12px">rtl/common/reset_sync.sv</td><td>no testbench references `reset_sync` — CLAUDE.md §4 requires a testbench for every fast-path module</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">coverage</td><td class="mono" style="font-size:12px">rtl/common/rr_arbiter.sv</td><td>no testbench references `rr_arbiter` — CLAUDE.md §4 requires a testbench for every fast-path module</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">coverage</td><td class="mono" style="font-size:12px">rtl/common/sync_fifo.sv</td><td>no testbench references `sync_fifo` — CLAUDE.md §4 requires a testbench for every fast-path module</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">coverage</td><td class="mono" style="font-size:12px">rtl/ctrl/csr_regfile.sv</td><td>no testbench references `csr_regfile` — CLAUDE.md §4 requires a testbench for every fast-path module</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">coverage</td><td class="mono" style="font-size:12px">rtl/ctrl/dma_log_ring.sv</td><td>no testbench references `dma_log_ring` — CLAUDE.md §4 requires a testbench for every fast-path module</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">coverage</td><td class="mono" style="font-size:12px">rtl/ctrl/host_ctrl.sv</td><td>no testbench references `host_ctrl` — CLAUDE.md §4 requires a testbench for every fast-path module</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">coverage</td><td class="mono" style="font-size:12px">rtl/ctrl/pcie_wrapper.sv</td><td>no testbench references `pcie_wrapper` — CLAUDE.md §4 requires a testbench for every fast-path module</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">coverage</td><td class="mono" style="font-size:12px">rtl/eth/eth_10g_wrapper.sv</td><td>no testbench references `eth_10g_wrapper` — CLAUDE.md §4 requires a testbench for every fast-path module</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">coverage</td><td class="mono" style="font-size:12px">rtl/eth/gt_wrapper_stub.sv</td><td>no testbench references `gt_wrapper_stub` — CLAUDE.md §4 requires a testbench for every fast-path module</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">coverage</td><td class="mono" style="font-size:12px">rtl/formal/fv_axis_props.sv</td><td>no testbench references `fv_axis_props` — CLAUDE.md §4 requires a testbench for every fast-path module</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">coverage</td><td class="mono" style="font-size:12px">rtl/order/ouch_rx.sv</td><td>no testbench references `ouch_rx` — CLAUDE.md §4 requires a testbench for every fast-path module</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">coverage</td><td class="mono" style="font-size:12px">rtl/order/tcp_tx_lite.sv</td><td>no testbench references `tcp_tx_lite` — CLAUDE.md §4 requires a testbench for every fast-path module</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">coverage</td><td class="mono" style="font-size:12px">rtl/strategy/position_track.sv</td><td>no testbench references `position_track` — CLAUDE.md §4 requires a testbench for every fast-path module</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">coverage</td><td class="mono" style="font-size:12px">rtl/strategy/trade_gate.sv</td><td>no testbench references `trade_gate` — CLAUDE.md §4 requires a testbench for every fast-path module</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">coverage</td><td class="mono" style="font-size:12px">rtl/telemetry/latency_hist.sv</td><td>no testbench references `latency_hist` — CLAUDE.md §4 requires a testbench for every fast-path module</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">header</td><td class="mono" style="font-size:12px">rtl/ctrl/csr_regfile.sv</td><td>module header missing `LATENCY` (CLAUDE.md §4)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">header</td><td class="mono" style="font-size:12px">rtl/ctrl/dma_log_ring.sv</td><td>module header missing `LATENCY` (CLAUDE.md §4)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">header</td><td class="mono" style="font-size:12px">rtl/ctrl/pcie_wrapper.sv</td><td>module header missing `LATENCY` (CLAUDE.md §4)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">header</td><td class="mono" style="font-size:12px">rtl/eth/crc32_eth.sv</td><td>module header missing `LATENCY` (CLAUDE.md §4)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">header</td><td class="mono" style="font-size:12px">rtl/eth/eth_10g_wrapper.sv</td><td>module header missing `LATENCY` (CLAUDE.md §4)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">header</td><td class="mono" style="font-size:12px">rtl/eth/gt_wrapper_stub.sv</td><td>module header missing `LATENCY` (CLAUDE.md §4)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">header</td><td class="mono" style="font-size:12px">rtl/eth/mac_rx.sv</td><td>module header missing `LATENCY` (CLAUDE.md §4)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">header</td><td class="mono" style="font-size:12px">rtl/eth/mac_tx.sv</td><td>module header missing `LATENCY` (CLAUDE.md §4)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">header</td><td class="mono" style="font-size:12px">rtl/feed/feed_handler.sv</td><td>module header missing `LATENCY` (CLAUDE.md §4)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">header</td><td class="mono" style="font-size:12px">rtl/feed/venue_state.sv</td><td>module header missing `LATENCY` (CLAUDE.md §4)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">header</td><td class="mono" style="font-size:12px">rtl/order/credit_mgr.sv</td><td>module header missing `LATENCY` (CLAUDE.md §4)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">header</td><td class="mono" style="font-size:12px">rtl/order/ouch_rx.sv</td><td>module header missing `LATENCY` (CLAUDE.md §4)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">header</td><td class="mono" style="font-size:12px">rtl/order/soupbin_tx.sv</td><td>module header missing `LATENCY` (CLAUDE.md §4)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">header</td><td class="mono" style="font-size:12px">rtl/order/tcp_tx_lite.sv</td><td>module header missing `LATENCY` (CLAUDE.md §4)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">header</td><td class="mono" style="font-size:12px">rtl/risk/position_monitor.sv</td><td>module header missing `LATENCY` (CLAUDE.md §4)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">header</td><td class="mono" style="font-size:12px">rtl/risk/rate_limiter.sv</td><td>module header missing `LATENCY` (CLAUDE.md §4)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">header</td><td class="mono" style="font-size:12px">rtl/risk/risk_params.sv</td><td>module header missing `LATENCY` (CLAUDE.md §4)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">header</td><td class="mono" style="font-size:12px">rtl/strategy/param_table.sv</td><td>module header missing `LATENCY` (CLAUDE.md §4)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">header</td><td class="mono" style="font-size:12px">rtl/strategy/position_track.sv</td><td>module header missing `LATENCY` (CLAUDE.md §4)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">header</td><td class="mono" style="font-size:12px">rtl/strategy/trade_gate.sv</td><td>module header missing `LATENCY` (CLAUDE.md §4)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/book/price_levels.sv:126</td><td>possible division — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/common/clk_rst_gen.sv:113</td><td>possible division — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/common/clk_rst_gen.sv:114</td><td>possible division — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/common/clk_rst_gen.sv:115</td><td>possible division — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/common/clk_rst_gen.sv:119</td><td>possible division — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/common/prio_encoder.sv:92</td><td>possible division — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/ctrl/pcie_wrapper.sv:95</td><td>possible division — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/eth/crc32_eth.sv:87</td><td>possible division — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/eth/crc32_eth.sv:88</td><td>possible division — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/eth/eth_10g_wrapper.sv:208</td><td>possible division — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/eth/gt_wrapper_stub.sv:139</td><td>possible division — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/eth/mac_rx.sv:173</td><td>possible division — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/eth/mac_tx.sv:142</td><td>possible division — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/net/eth_ip_udp_rx.sv:147</td><td>possible division — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/net/eth_ip_udp_rx.sv:148</td><td>possible modulo — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/net/eth_ip_udp_rx.sv:149</td><td>possible modulo — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/net/eth_ip_udp_rx.sv:150</td><td>possible division — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/net/eth_ip_udp_rx.sv:151</td><td>possible modulo — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/net/eth_ip_udp_rx.sv:152</td><td>possible modulo — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/net/eth_ip_udp_rx.sv:153</td><td>possible division — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/net/eth_ip_udp_rx.sv:154</td><td>possible modulo — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/net/eth_ip_udp_rx.sv:155</td><td>possible division — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/net/eth_ip_udp_rx.sv:157</td><td>possible modulo — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/net/eth_ip_udp_rx.sv:158</td><td>possible modulo — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/net/eth_ip_udp_rx.sv:163</td><td>possible division — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/net/eth_ip_udp_rx.sv:165</td><td>possible modulo — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/order/ouch_encoder.sv:183</td><td>possible division — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/order/ouch_encoder.sv:190</td><td>possible division — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr><tr class="sev sev-warn"><td><span class="chip warn">warn</span></td><td class="mono dim">rtl-discipline</td><td class="mono" style="font-size:12px">rtl/risk/risk_params.sv:165</td><td>possible division — no dividers on the fast path (manuals/00-foundations/03 §7)</td></tr></tbody>
</table></div>
</section>
<div class="callout">
<p><b>What this report proves.</b> The repository is internally consistent: every module
the top level instantiates exists, every cross-reference resolves, and the RTL obeys the
coding rules in <code>CLAUDE.md</code>.</p>
<p><b>What it does not prove.</b> That the design is correct, or fast. Correctness requires
simulating the order book against the golden software model over a real market-data corpus.
Speed requires a post-route timing report and an external wire-to-wire measurement.
<b>Every latency figure in this repository is currently a design target, not a measurement</b> —
nothing here has run on hardware.</p>
</div>
<footer>
re-run: python3 scripts/validate.py --html docs/validation-report.html<br>
ERROR findings are build-blocking; WARN findings are advisory.
</footer>
</div>