add index bitwidth=10 (#181)

add index bitwidth=10

Author: YangWang92

csrc/dequant.cu

@@ -63,6 +63,9 @@ namespace vptq {
     case 12:                                                                   \
       callDequantWithOutliers_dtype(12, BASEGROUP, OUT_OUF_INF, ResidualBits); \
       break;                                                                   \
+    case 10:                                                                   \
+      callDequantWithOutliers_dtype(10, BASEGROUP, OUT_OUF_INF, ResidualBits); \
+      break;                                                                   \
     case 8:                                                                    \
       callDequantWithOutliers_dtype(8, BASEGROUP, OUT_OUF_INF, ResidualBits);  \
       break;                                                                   \
@@ -200,6 +203,7 @@ torch::Tensor launch_deqantize_outliers_cuda_packkernel(
   switch (base_groupsize) {
     CASE_DispatchDequantWithOutliers(16);
     CASE_DispatchDequantWithOutliers(12);
+    CASE_DispatchDequantWithOutliers(10);
     CASE_DispatchDequantWithOutliers(8);
     CASE_DispatchDequantWithOutliers(6);
     CASE_DispatchDequantWithOutliers(4);

csrc/quant_gemv.cu

@@ -67,6 +67,9 @@ namespace vptq {
     case 12:                                                                  \
       CallWqA16kernel_dtype(out_buf, 12, BASEGROUP, Do_Reduce, ResidualBits); \
       break;                                                                  \
+    case 10:                                                                  \
+      CallWqA16kernel_dtype(out_buf, 10, BASEGROUP, Do_Reduce, ResidualBits); \
+      break;                                                                  \
     case 8:                                                                   \
       CallWqA16kernel_dtype(out_buf, 8, BASEGROUP, Do_Reduce, ResidualBits);  \
       break;                                                                  \
@@ -209,6 +212,9 @@ torch::Tensor launch_gemv_outliers_cuda_packkernel(
       case 12:
         DispatchWqA16Kernel(tmp_output, 12, do_reduce);
         break;
+      case 10:
+        DispatchWqA16Kernel(tmp_output, 10, do_reduce);
+        break;
       case 8:
         DispatchWqA16Kernel(tmp_output, 8, do_reduce);
         break;

pyproject.toml

@@ -1,6 +1,6 @@
 [project]
 name = "vptq"
-version = "0.0.5"
+version = "0.0.5post1"
 authors = [
   { name="Ying Cao", email="lcy.seso@gmail.com" },
   { name="Jicheng Wen", email="wejoincy@gmail.com" },