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[0035] Fix order, name, and missing param of VecAccum
1 parent c2f44e3 commit 5232acc

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Lines changed: 17 additions & 15 deletions

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proposals/0035-linalg-matrix.md

Lines changed: 17 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -286,8 +286,8 @@ OuterProduct(vector<InputElTy, M> VecA, vector<InputElTy, N> VecB);
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template <typename InputElTy, SIZE_TYPE M>
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typename hlsl::enable_if<hlsl::is_arithmetic<InputElTy>::value, void>::type
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InterlockedAccumulate(vector<InputElTy, M> Vec, RWByteAddressBuffer Res,
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uint StartOffset);
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InterlockedAccumulate(RWByteAddressBuffer Res, vector<InputElTy, M> Vec,
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uint StartOffset, uint Align = 64);
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} // namespace linalg
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} // namespace dx
@@ -1081,8 +1081,8 @@ provided matrix argument into the accumulator matrix.
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```c++
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template <typename InputElTy, SIZE_TYPE M>
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typename hlsl::enable_if<hlsl::is_arithmetic<InputElTy>::value, void>::type
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InterlockedAccumulate(vector<InputElTy, M> Vec, RWByteAddressBuffer Res,
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uint StartOffset);
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InterlockedAccumulate(RWByteAddressBuffer Res, vector<InputElTy, M> Vec,
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uint StartOffset, uint Align = 64);
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```
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Atomically adds the vector data of `Vec` to the `RWByteAddressBuffer` target
@@ -1583,7 +1583,7 @@ declare <[NUMo] x [TYo]> @dx.op.linAlgMatVecMul.v[NUMo][TYo].[MatTy].v[NUMi][TYi
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immarg i1, ; is output signed
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<[NUMi] x [TYi]>, ; input vector
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immarg i32 ; input interpretation type (DXIL::ComponentType)
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)
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)
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```
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This operation implements a column-vector multiplication against an `A` matrix
@@ -1607,7 +1607,7 @@ declare <[NUMo] x [TYo]> @dx.op.linAlgMatVecMulAdd.v[NUMo][TYo].[MatTy].v[NUMi][
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immarg i32, ; input interpretation type (DXIL::ComponentType)
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<[NUMo] x [TYb]>, ; bias vector
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immarg i32 ; bias interpretation type (DXIL::ComponentType)
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)
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)
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```
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This operation implements a column-vector multiplication against an `A` matrix
@@ -1695,7 +1695,7 @@ declare <[NUMo] x [TYo]> @dx.op.linAlgConvert.v[NUMo][TYo].v[NUMi][TYi](
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<[NUMi] x [TYi]>, ; input vector
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immarg i32, ; input interpretation type (DXIL::ComponentType)
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immarg i32 ; output interpretation type (DXIL::ComponentType)
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)
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)
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```
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Converts an input vector containing data of the input interpretation type to a
@@ -1776,11 +1776,13 @@ represent all values of the format used in the shader's DXIL.
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> FP type, this may cause expected behavior differences.
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``` llvm
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declare void @dx.op.vectorAccumulateToDescriptor.v[NUM][TY](
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immarg i32, ; opcode
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<[NUM] x [TY]>, ; input vector
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%dx.types.Handle, ; destination RWByteAddressBuffer
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i32) ; buffer offset
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declare void @dx.op.linAlgVectorAccumulateToDescriptor.v[NUM][TY](
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immarg i32, ; opcode
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<[NUM] x [TY]>, ; input vector
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%dx.types.Handle, ; destination RWByteAddressBuffer
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i32, ; buffer offset
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i32 ; vector element alignment
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)
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```
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Accumulates a vector to a RWByteAddressBuffer at a specified offset. Each
@@ -1801,7 +1803,7 @@ elements to the default value.
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The `@dx.op.linAlgMatrixStoreToDescriptor`,
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`@dx.op.linAlgMatrixAccumulateToDescriptor`, and
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`@dx.op.vectorAccumulateToDescriptor` operations write data to a
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`@dx.op.linAlgVectorAccumulateToDescriptor` operations write data to a
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descriptor. Writes to out of bounds memory are a no-op. An implementation may
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either perform bounds checking on the full bounds of the store converting the
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whole store to a no-op if any elelemt is out of bounds, or it may perform
@@ -2266,8 +2268,8 @@ OuterProduct(vector<InputElTy, M> VecA, vector<InputElTy, N> VecB);
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template <typename InputElTy, SIZE_TYPE M>
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typename hlsl::enable_if<hlsl::is_arithmetic<InputElTy>::value, void>::type
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InterlockedAccumulate(vector<InputElTy, M> Vec, RWByteAddressBuffer Res,
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uint StartOffset);
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InterlockedAccumulate(RWByteAddressBuffer Res, vector<InputElTy, M> Vec,
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uint StartOffset, uint Align = 64);
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} // namespace linalg
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} // namespace dx

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