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| 1 | +# Spec 047 §14 Phase 3 — final bulk-port, x64 advisory |
| 2 | + |
| 3 | +**This is an advisory x64 capture, NOT authoritative.** Cloud PC |
| 4 | +(`CPC-ander-YTZ3O`, AMD EPYC 7763 64-Core Processor, x64), not on |
| 5 | +AC/dedicated hardware. Do not cite these numbers in §13 or §14 spec |
| 6 | +text. A stable-AC ARM64 re-capture on `LAPTOP-4MEP83VI` should ratify |
| 7 | +the matrix before §14 Phase 3 is closed. |
| 8 | + |
| 9 | +## Why this capture exists |
| 10 | + |
| 11 | +This run extends the `2026-05-27-batch-1-2-3x5/` matrix with the |
| 12 | +remaining Phase 3 batches landed in the bulk-port PR |
| 13 | +(`spec/047-phase3-bulk-port`): |
| 14 | + |
| 15 | +- **Batch 3** — Display family (TextBlock, Image, PersonPicture, |
| 16 | + ProgressBar, ProgressRing, InfoBadge). |
| 17 | +- **Batch 4** — Button family (Button, HyperlinkButton, RepeatButton, |
| 18 | + ToggleButton, DropDownButton, SplitButton). |
| 19 | +- **Batch 5** — Value-bearing inputs (RichEditBox, PasswordBox, |
| 20 | + RadioButtons). |
| 21 | +- **Batch 6** — Multi-event inputs (AutoSuggestBox, ComboBox). |
| 22 | +- **Batch 7** — Single-content containers (Viewbox, Expander, |
| 23 | + ScrollViewer, ScrollView). |
| 24 | +- **Batch 8** — Panels (StackPanel, Grid, Canvas, FlexPanel, |
| 25 | + RelativePanel). |
| 26 | +- **Batch 9** — Named-slot containers (SplitView, InfoBar, TeachingTip). |
| 27 | +- **Batch 10** — Shapes + display leaves (Rectangle, Ellipse, Line, |
| 28 | + Path, AnimatedIcon). |
| 29 | +- **Batch 11** — Long tail (PipsPager, ListBox, SelectorBar, |
| 30 | + BreadcrumbBar). |
| 31 | + |
| 32 | +After all batches the `DescriptorVariantFactory` registers **50 ported |
| 33 | +controls** (12 from prior PRs: 4 prereq + 8 batches 1+2; 38 new from |
| 34 | +batches 3-11). The bench matrix detects dispatch-table shape change |
| 35 | +and descriptor-interpreter amortization across M1-M13 even though |
| 36 | +those benches don't mount the new controls directly. |
| 37 | + |
| 38 | +## Capture environment |
| 39 | + |
| 40 | +`CPC-ander-YTZ3O`, x64 (AMD EPYC 7763 64-Core Processor), Release, |
| 41 | +.NET 10.0.8, Windows 11 26200. **Cloud PC — not on AC/dedicated |
| 42 | +hardware**. 3 process launches × 5 reps × 13 benches × 4 variants = |
| 43 | +780 measurements across `launch-1.jsonl` + `launch-2.jsonl` + |
| 44 | +`launch-3.jsonl`. |
| 45 | + |
| 46 | +## Headline — V1 ON (descriptors) vs V1 OFF (today) |
| 47 | + |
| 48 | +The user-facing question is "does turning V1 ON with the full Phase 3 |
| 49 | +descriptor set regress anything." Median of n=15 (3 launches × 5 reps) |
| 50 | +per cell: |
| 51 | + |
| 52 | +| Bench | V1 ON (Descriptors) vs V1 OFF (Today) | Verdict | |
| 53 | +|---|---:|---| |
| 54 | +| M1 Mount_Leaf_NoCallback | **+14.9%** | exceeds 5-15% judgment-call band ceiling | |
| 55 | +| M2 Mount_Leaf_OneCallback | -1.7% | within noise | |
| 56 | +| M3 Mount_Leaf_ThreeCallbacks | +3.3% | within noise | |
| 57 | +| M4 Dispatch_Switch_Cold | **-21.2%** | improvement (fewer types fall through to switch arm) | |
| 58 | +| M5 Dispatch_Switch_Warm | **-24.3%** | improvement (same; warmer dispatch hits handler table) | |
| 59 | +| M6 Dispatch_ExternalType | +0.2% | within noise | |
| 60 | +| M7 Update_NoChange | +7.4% | judgment-call band | |
| 61 | +| M8 Update_OneLeafChanged | **+25.5%** | **largest regression** | |
| 62 | +| M9 Update_AllChanged | +3.6% | within noise | |
| 63 | +| M10 EventHandlerState_Alloc | +8.7% | judgment-call band | |
| 64 | +| M11 ModifierEHS_Frequency | +8.5% | judgment-call band | |
| 65 | +| M12 Pool_Rent_HotPath | **+20.9%** | second-largest regression | |
| 66 | +| M13 Setters_Suppression_Scope | -0.9% | within noise | |
| 67 | + |
| 68 | +**The +25.5% on M8 (Update_OneLeafChanged) and +20.9% on M12 |
| 69 | +(Pool_Rent_HotPath) exceed the §13 Q1 5-15% judgment-call band.** |
| 70 | +This is a real surfacing of descriptor-interpreter Update overhead |
| 71 | +compared to the hand-coded switch arms, now amortized over 50 |
| 72 | +registered controls. |
| 73 | + |
| 74 | +The M4/M5 improvements are the mirror image: dispatch is faster when |
| 75 | +more types are in the handler table (the fallback to the switch arm |
| 76 | +is rarer). Net Mount cost is dominated by interpreter overhead (M1 |
| 77 | ++14.9%); net Update cost regresses substantially on one-leaf-change |
| 78 | +workloads (M8 +25.5%). |
| 79 | + |
| 80 | +These deltas reproduce the trade-off the §13 Q1 stable-AC capture |
| 81 | +already documented (M2 +9.6% at batch-2 scope). The 5-percentage-point |
| 82 | +shift on the M1/M5 readings between this capture and the prior |
| 83 | +`2026-05-27-batch-1-2-3x5/` capture is consistent with the prior |
| 84 | +README's "noise-prone, advisory" caveat — Cloud PC, no AC pinning. |
| 85 | + |
| 86 | +## Q1 decision matrix — for completeness |
| 87 | + |
| 88 | +Per §13 Q1's pre-committed decision matrix applied to |
| 89 | +ReactorDescriptors vs ReactorV2: |
| 90 | + |
| 91 | +| Bench | vs ReactorV2 ns | Q1 band | |
| 92 | +|---|---:|---| |
| 93 | +| M1 | +19.6% | exceeds 15% — judgment call vs LOC/readability | |
| 94 | +| M2 | -5.5% | ship descriptors | |
| 95 | +| M5 | -18.6% | ship descriptors (improvement) | |
| 96 | +| M7 | +7.7% | judgment-call band | |
| 97 | +| M10 | +2.4% | ship descriptors | |
| 98 | + |
| 99 | +**Verdict:** No reopen condition for Q1 — Q1's reopen is gated on |
| 100 | +source-gen (§7) landing, not advisory perf noise. The scope-amortized |
| 101 | +deltas on M1/M8/M12 should be confirmed on stable-AC ARM64 before any |
| 102 | +spec-text change. |
| 103 | + |
| 104 | +## Caveats |
| 105 | + |
| 106 | +- **Cloud PC noise.** Per the prior README: "noise-prone, advisory. |
| 107 | + Do not cite in §13/§14 spec text." |
| 108 | +- **ARM64 stable-AC re-capture on `LAPTOP-4MEP83VI` is deferred** from |
| 109 | + this session (not on critical path; tracked for spec close-out |
| 110 | + alongside the §14 Phase 3 ratification gate). |
| 111 | +- M7 (Update_NoChange) Direct measurement is dominated by the |
| 112 | + 3-second `Stopwatch` calibration in BenchRunner — Direct timing on |
| 113 | + this no-op bench is degenerate; only the relative |
| 114 | + Today/V2/Descriptors comparison is meaningful. |
| 115 | + |
| 116 | +## Reproduce |
| 117 | + |
| 118 | +```powershell |
| 119 | +cd C:\Users\andersonch\Code\reactor2 |
| 120 | +dotnet build tests/perf_bench/PerfBench.ControlModel -c Release -p:Platform=x64 |
| 121 | +# 3 launches: |
| 122 | +1..3 | ForEach-Object { |
| 123 | + & tests/perf_bench/PerfBench.ControlModel/bin/x64/Release/net10.0-windows10.0.22621.0/PerfBench.ControlModel.exe |
| 124 | + Copy-Item tests/perf_bench/PerfBench.ControlModel/bin/x64/Release/net10.0-windows10.0.22621.0/results.jsonl ` |
| 125 | + docs/specs/047/phase3-results/CPC-ander-YTZ3O-x64-advisory/2026-05-27-phase3-final-3x5/launch-$_.jsonl |
| 126 | +} |
| 127 | +``` |
| 128 | + |
| 129 | +Aggregation: median across (benchId, variant) over the three launches. |
| 130 | +See `summary.md` for the full per-bench table. |
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