Commit 6855ada
spec(047): Phase 0 deliverables — audits, perf scaffolding, ARM64 baseline
Lands the seven Phase 0 deliverables from spec §14 so 047 can clear its
exit gate. Audit results, perf-suite infrastructure, ARM64-native
baseline measurements, decision criteria, and the factoring
recommendation are all under docs/specs/047/.
Audits (0.1, 0.2, 0.5):
- BeginSuppress audit — 24 call sites classified (14 eliminable, 8
tolerance-shaped, 1 ColorPicker §8.1 edge case, 1 redundant). CSV +
one-page summary; spec §8 footnotes the audit.
- EventHandlerState field audit — 51 fields classified (42 routed-input,
9 control-intrinsic across 7 controls). Per-control struct sketches
for §9.2.
- Existing-API surface inventory — promote-vs-stay-internal table for
Phase 1's first task. 8 in-tree RegisterType call sites enumerated.
Perf suite (0.3):
- StressPerf.ReactorV2 + BlankReactorV2 — verbatim copies of the
Reactor variants at Phase-0 freeze; built and shipping ARM64-native
retail. V2 numbers ≈ Today numbers so Phase 1+ work shows up as the
delta.
- PerfBench.ControlModel — new WinUI host project implementing M1–M13
across Direct/ReactorToday/ReactorV2 variants. CLI for selective
runs + a --demo mode that captures one screenshot per (bench,
variant) via win32 PrintWindow.
- tools/spec047-aggregator — JSON-Lines → §15.6 (a)/(b)/(c) markdown
tables + trend.csv. Rejects rows missing required environment
metadata.
- perf-suite-runbook.md — operator-side environment-isolation rules
(foreground, AC, DRR off, no session switches, High Performance
power plan, warm-up policy). Cross-references the prior stress_perf
memory entries.
Baseline (0.4):
- ARM64-native retail M1–M13 captured on LAPTOP-4MEP83VI (Snapdragon X).
195 result rows, 0 excluded. Aggregator output committed under
baseline-results/LAPTOP-4MEP83VI/2026-05-25-arm64/aggregator-out/.
- 39 PrintWindow screenshots — one per (bench, variant) — confirm each
scenario actually exercises WinUI rendering (M13 visually shows the
§8.2 bug: ToggleSwitch ends up On after Set, callback fires).
- Reference x64-emulated capture preserved under .../2026-05-25/ as a
negative control; ARM-on-ARM is ~8–17× faster on the same silicon
for mount/dispatch-dominated tests.
- Spec §11.6 target table rewritten against measured M1–M3 with
Target = min(Direct + 100, ReactorToday × 0.4). Spec §12 opening
footnotes the Phase-0 anchor.
Decision criteria + factoring (0.6, 0.7):
- decision-criteria.md ratifies Q1/Q3/Q6/Q7/Q11/Q17/Q18/Q19 with
thresholds keyed to the audit data and the M-bench gates.
- factoring-recommendation.md: keep 047 unified; the only carve-out
is a standalone §8.2 setter-suppression fix (small, ahead of Phase 1).
Macros (0.3.4):
- L1 ships three-way (BlankWinUI3 + BlankReactor + BlankReactorV2);
run_startup_bench.ps1 enumerates the V2 variant. L2/L3 scenario
contracts frozen in macro-suite-status.md; binary implementations and
L4/L5/L7–L9/L11 deferred to Phase 1 with explicit rationale.
This commit clears the Phase 0 exit gate (spec §14): all seven
deliverables complete, baseline numbers committed, §11/§12 updated with
measured numbers, factoring reviewed and ratified.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>1 parent 0f739c3 commit 6855ada
84 files changed
Lines changed: 4856 additions & 7 deletions
File tree
- docs/specs
- 047
- audits
- baseline-results
- LAPTOP-4MEP83VI
- 2026-05-25-arm64
- aggregator-out
- screenshots
- 2026-05-25
- aggregator-out
- tasks
- tests
- perf_bench/PerfBench.ControlModel
- Benches
- Variants
- startup_perf
- BlankReactorV2
- stress_perf/StressPerf.ReactorV2
- tools/spec047-aggregator
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