From 1abea26acc001ba9f255f04629ab02114fdd8cbc Mon Sep 17 00:00:00 2001 From: Chris Anderson Date: Fri, 29 May 2026 23:30:31 -0700 Subject: [PATCH 1/2] =?UTF-8?q?spec-047=20=C2=A74.9:=20ARM64=20post-Phase-?= =?UTF-8?q?4=20micro=20perf=20capture=20(LAPTOP-4MEP83VI)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Indicative M1–M13 capture on the §4.9 baseline box, ARM64-native/Release/.NET 10.0.8, reps=5, iters matched to the 2026-05-25 baseline (M1–M8 @5000, M9 @2000, M10–M13 @1000). Adds raw JSONL, the aggregator-out tables, RESULTS.md (cross- baseline comparison), and analyze.py. Allocation (deterministic, valid — Direct alloc matches baseline byte-for-byte): - §15.6 "M1–M3 alloc ≤ Today": M2 −5%, M3 −6% PASS; M1 +20% FAIL. - §11.6 byte gates: M3 PASS; M1 (3.2×) and M2 (2.4×) over target. - vs baseline ReactorV2: most benches flat/better (M9 −41% standout); M1 +20% and M12 +17% are real, deterministic regressions to investigate. Confirms the KD-3 trigger (M1 over budget). NOT a ratification sign-off: §15.5 isolation (AC/High-Perf/DRR/foreground) was not enforced, so the timing axis is environment-throttled (Direct ns +60–140% vs baseline) and must be disregarded; the §4.9 randomized/interleaved ordering + CPU-clock telemetry is not wired; and the macro suite (L1–L14) is unrunnable (its projects were deleted in Phase 4). Co-Authored-By: Claude Opus 4.8 (1M context) --- .../2026-05-29-arm64/RESULTS.md | 108 ++++++++++ .../aggregator-out/excluded.txt | 0 .../aggregator-out/summary-absolute.md | 19 ++ .../aggregator-out/summary-delta.md | 19 ++ .../aggregator-out/summary-gap.md | 19 ++ .../2026-05-29-arm64/aggregator-out/trend.csv | 196 ++++++++++++++++++ .../2026-05-29-arm64/analyze.py | 103 +++++++++ .../perfbench-controlmodel-m1-m8.jsonl | 120 +++++++++++ .../perfbench-controlmodel-m10-m13.jsonl | 60 ++++++ .../perfbench-controlmodel-m9.jsonl | 15 ++ 10 files changed, 659 insertions(+) create mode 100644 docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/RESULTS.md create mode 100644 docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/aggregator-out/excluded.txt create mode 100644 docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/aggregator-out/summary-absolute.md create mode 100644 docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/aggregator-out/summary-delta.md create mode 100644 docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/aggregator-out/summary-gap.md create mode 100644 docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/aggregator-out/trend.csv create mode 100644 docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/analyze.py create mode 100644 docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/perfbench-controlmodel-m1-m8.jsonl create mode 100644 docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/perfbench-controlmodel-m10-m13.jsonl create mode 100644 docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/perfbench-controlmodel-m9.jsonl diff --git a/docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/RESULTS.md b/docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/RESULTS.md new file mode 100644 index 00000000..3531d4cf --- /dev/null +++ b/docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/RESULTS.md @@ -0,0 +1,108 @@ +# Spec-047 Post-Phase-4 Perf Capture — vs 2026-05-25 ARM64 baseline + +**Machine:** `LAPTOP-4MEP83VI` (Qualcomm ARMv8, the spec-047 §4.9 baseline box) +**Arch/Runtime:** ARM64-native, Release, .NET 10.0.8 — identical to baseline +**Date:** 2026-05-30 (UTC) · **Branch:** `main` (all of spec-047 incl. Phase 4 merged) +**Suite:** micro M1–M13 (`PerfBench.ControlModel`), reps=5, iters matched to baseline +(M1–M8 @5000, M9 @2000, M10–M13 @1000). 195 rows, 0 errors. + +> ⚠️ **Scope caveat — this is an INDICATIVE capture, not the formal §4.9 ratification.** +> The §15.5 environment-isolation requirements (AC power, High-Performance plan, DRR +> off, foreground non-occluded window) could **not** be enforced from this automated +> run, and the harness does not yet implement the §4.9-required randomized/interleaved +> variant ordering + CPU-clock telemetry. **Consequence: the timing (ns) numbers are +> environment-contaminated and must be disregarded** for cross-baseline comparison — +> the `Direct` variant (pure WinUI, *zero* Reactor code) is itself inflated +60–140% +> vs the baseline run, which can only be thermal/power throttling. **The allocation +> (bytes) numbers ARE valid**: managed allocation is deterministic and +> environment-independent — confirmed by `Direct` alloc matching the baseline +> byte-for-byte (M1 Direct = 3,771,824 B in both runs). + +--- + +## Headline findings (allocation — the valid, deterministic axis) + +The macro suite (L1–L14: TTFF / working-set / FPS / GC) is **not runnable** — Phase 4 +deleted its projects (`StressPerf.ReactorV2`, `BlankReactorV2`). So only the §15.6 +micro budgets (per-element alloc M1–M3, dispatch M4–M6, update M7–M8) are covered here. + +### 1. §15.6 "M1–M3 per-element alloc must improve/equal Today" — **M1 FAILS** + +| Bench | Reactor (new) B/render | Today (base) B/render | Δ vs Today | Verdict | +|---|---:|---:|---:|:--| +| **M1** TextBlock, no callback | **1,289** | 1,071 | **+20.3%** | ❌ **regressed** | +| M2 ToggleSwitch, 1 callback | 3,687 | 3,884 | −5.1% | ✅ improved | +| M3 Button + 2 pointer mods | 8,530 | 9,075 | −6.0% | ✅ improved | + +### 2. Phase-4 refactor impact: current `Reactor` vs **baseline `ReactorV2`** (same V1 lineage) + +This isolates what the post-baseline Phase-4 work (`ElementExtras` bucketing §4.4, +EHS split §4.3, echo hybrid §4.2) did to the V1 path's allocation: + +| Bench | new B/render | base-V2 B/render | Δ | Note | +|---|---:|---:|---:|:--| +| **M1** | **1,289** | 1,077 | **+19.6%** | ❌ leanest leaf got **heavier** | +| M2 | 3,687 | 3,864 | −4.6% | ✅ | +| M3 | 8,530 | 8,633 | −1.2% | ≈ flat | +| M4 | 1,941 | 1,998 | −2.8% | ✅ | +| M5 | 1,948 | 2,212 | −11.9% | ✅ | +| M6 | 888 | 941 | −5.6% | ✅ | +| M7 | 252 | 156 | +61.4% | tiny absolute (+96 B) | +| M8 | 362 | 425 | −14.9% | ✅ | +| **M9** | 184,431 | 312,246 | **−40.9%** | ✅ big win (keyed list) | +| M10 | 3,411 | 3,949 | −13.6% | ✅ | +| M11 | 1,641 | 1,670 | −1.7% | ✅ (per-element state) | +| **M12** | 1,273 | 1,088 | **+17.0%** | ❌ pool-reuse regressed | +| M13 | 29 | 29 | −0.4% | ≈ flat | + +The M1 regression is **deterministic, not noise**: every new rep (6.34–6.51 MB) +sits uniformly above every baseline rep (5.25–5.42 MB) — a consistent ~+235 B/render. +Likely sources to investigate: the added `Element.Extensions` slot on every element, +the §4.3 EHS-split, or the `ReactorState.PendingEchoMatch` slot on the mount path. +M12 (pool rent/return) similarly regressed +17%. + +### 3. §11.6 absolute byte-gate (`PerformanceBudgets.cs`) — **M1, M2 FAIL** + +| Bench | Target | Reactor (new) B/render | Pass? | +|---|---:|---:|:---:| +| M1 | ≤ 407 | 1,289 | ❌ (3.2×) | +| M2 | ≤ 1,520 | 3,687 | ❌ (2.4×) | +| M3 | ≤ 19,200 | 8,530 | ✅ | + +Note the gate targets were defined as `baseline × 0.4`, but the *measured* ARM64 +baselines were ~1,077 / 3,864 / 8,633 — so M1/M2 never had a realistic path to +407/1,520 without the deferred KD-3 binder-check fold + further leaf-alloc work, and +M3's 19,200 target was already cleared at baseline. **The byte gates as written are +not met for M1/M2.** This directly confirms the spec's own KD-3 trigger condition +("fold the M1 leading-`if` binder check … if M1 is still above budget after §4.3/§4.4") +— M1 *is* over budget, so that follow-up is now warranted. + +--- + +## Timing (ns) — captured but NOT comparable cross-baseline + +Disregard for ratification. Evidence of environment contamination (identical `Direct` +code, new vs baseline ns): M3 +139%, M4 +130%, M5 +60%, M7 +940µs absolute swing. +Within-run `Reactor`-vs-`Direct` overhead is directionally consistent with baseline +(Reactor adds dispatch cost on M1–M6, wins big on M7/M9 via pooling) but the absolute +numbers are throttled and should be re-captured under §15.5 isolation before any +timing-budget sign-off. + +--- + +## Bottom line for §4.9 + +- ✅ **Build + capture reproducible on the actual ARM64 baseline box**; allocation is + deterministic and matches baseline `Direct` byte-for-byte. +- ✅ **Most of the V1 path held or improved** vs the captured baseline on allocation + (M2/M3/M4/M5/M6/M8/M9/M10/M11), with a standout **−41% on M9** (keyed list). +- ❌ **Two allocation regressions to fix before claiming the byte-gate pass:** + **M1 +20%** (and 3.2× over its 407 B gate) and **M12 +17%**. +- ⛔ **Not a ratification sign-off:** timing axis is environment-throttled, the + §4.9-mandated randomized/interleaved ordering + CPU-clock telemetry isn't wired, + and the macro suite (L1–L14) can't run (projects deleted). A real §4.9 close needs + an isolated stable-AC re-capture (and the macro suite rebuilt against the single + `Reactor` variant). + +_Raw data: `perfbench-controlmodel-{m1-m8,m9,m10-m13}.jsonl` in this folder. +Analysis: `analyze.py`. Baseline: `docs/specs/047/baseline-results/LAPTOP-4MEP83VI/2026-05-25-arm64/`._ diff --git a/docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/aggregator-out/excluded.txt b/docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/aggregator-out/excluded.txt new file mode 100644 index 00000000..e69de29b diff --git a/docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/aggregator-out/summary-absolute.md b/docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/aggregator-out/summary-absolute.md new file mode 100644 index 00000000..c9856128 --- /dev/null +++ b/docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/aggregator-out/summary-absolute.md @@ -0,0 +1,19 @@ +# Spec 047 §15.6 (a) — Absolute Comparison + +Mean ns per op + alloc bytes, per variant. Columns are dashes when a variant has < min-reps repetitions. Architecture column distinguishes ARM64-native from x64-emulated runs (spec §15.5 — non-comparable across architectures). + +| Bench | Arch | Direct ns | Today ns | Reactor ns | Direct alloc | Today alloc | Reactor alloc | +|---|---|---:|---:|---:|---:|---:|---:| +| M1 | Arm64 | 35795.2 | 43113.7 | 43820.5 | 3771877 | 6410214 | 6442971 | +| M10 | Arm64 | 33549.5 | 44664.7 | 43450.0 | 2958312 | 3558654 | 3410949 | +| M11 | Arm64 | 33.9 | 38605.7 | 34239.4 | 40 | 1714131 | 1641088 | +| M12 | Arm64 | 25807.4 | 33245.4 | 34545.0 | 760114 | 1306086 | 1273350 | +| M13 | Arm64 | 35.5 | 106.8 | 220.6 | 24040 | 29373 | 29320 | +| M2 | Arm64 | 50476.4 | 112278.4 | 98428.2 | 13425966 | 18317597 | 18436637 | +| M3 | Arm64 | 422189.5 | 378451.1 | 390740.2 | 28890936 | 41535106 | 42649842 | +| M4 | Arm64 | 76426.5 | 144403.7 | 139003.5 | 4674357 | 10708440 | 9707059 | +| M5 | Arm64 | 34110.0 | 157595.6 | 134839.9 | 4674357 | 10736699 | 9741629 | +| M6 | Arm64 | 43099.6 | 59261.6 | 55663.5 | 3869357 | 4181165 | 4438270 | +| M7 | Arm64 | 1737075.3 | 22028.2 | 21858.9 | 122599664 | 996032 | 1258197 | +| M8 | Arm64 | 7617.1 | 9601.4 | 9258.0 | 915536 | 1807872 | 1807872 | +| M9 | Arm64 | 911654.9 | 3102404.2 | 2483238.8 | 96669803 | 368877754 | 368861339 | diff --git a/docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/aggregator-out/summary-delta.md b/docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/aggregator-out/summary-delta.md new file mode 100644 index 00000000..5e31513c --- /dev/null +++ b/docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/aggregator-out/summary-delta.md @@ -0,0 +1,19 @@ +# Spec 047 §15.6 (b) — Reactor Delta (Reactor vs Today) + +Positive % = Reactor slower / larger than Today. Negative = improvement. One row per (bench, architecture). + +| Bench | Arch | ns delta % | ns 95% CI half-width | alloc delta % | +|---|---|---:|---:|---:| +| M1 | Arm64 | +1.6% | ±5.1% | +0.5% | +| M10 | Arm64 | -2.7% | ±4.0% | -4.2% | +| M11 | Arm64 | -11.3% | ±4.4% | -4.3% | +| M12 | Arm64 | +3.9% | ±8.5% | -2.5% | +| M13 | Arm64 | +106.6% | ±220.6% | -0.2% | +| M2 | Arm64 | -12.3% | ±6.1% | +0.6% | +| M3 | Arm64 | +3.2% | ±23.9% | +2.7% | +| M4 | Arm64 | -3.7% | ±8.8% | -9.4% | +| M5 | Arm64 | -14.4% | ±16.3% | -9.3% | +| M6 | Arm64 | -6.1% | ±9.2% | +6.1% | +| M7 | Arm64 | -0.8% | ±4.8% | +26.3% | +| M8 | Arm64 | -3.6% | ±4.1% | 0.0% | +| M9 | Arm64 | -20.0% | ±23.3% | 0.0% | diff --git a/docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/aggregator-out/summary-gap.md b/docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/aggregator-out/summary-gap.md new file mode 100644 index 00000000..b33d39fb --- /dev/null +++ b/docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/aggregator-out/summary-gap.md @@ -0,0 +1,19 @@ +# Spec 047 §15.6 (c) — WinUI Gap (Reactor vs Direct) + +Absolute overhead Reactor still adds on top of raw WinUI. One row per (bench, architecture). + +| Bench | Arch | Reactor ns | Direct ns | Reactor - Direct ns | Reactor alloc - Direct alloc | +|---|---|---:|---:|---:|---:| +| M1 | Arm64 | 43820.5 | 35795.2 | +8025.4 | +2671094 | +| M10 | Arm64 | 43450.0 | 33549.5 | +9900.5 | +452637 | +| M11 | Arm64 | 34239.4 | 33.9 | +34205.5 | +1641048 | +| M12 | Arm64 | 34545.0 | 25807.4 | +8737.6 | +513237 | +| M13 | Arm64 | 220.6 | 35.5 | +185.1 | +5280 | +| M2 | Arm64 | 98428.2 | 50476.4 | +47951.8 | +5010670 | +| M3 | Arm64 | 390740.2 | 422189.5 | -31449.3 | +13758906 | +| M4 | Arm64 | 139003.5 | 76426.5 | +62577.0 | +5032702 | +| M5 | Arm64 | 134839.9 | 34110.0 | +100729.9 | +5067272 | +| M6 | Arm64 | 55663.5 | 43099.6 | +12563.8 | +568914 | +| M7 | Arm64 | 21858.9 | 1737075.3 | -1715216.4 | -121341467 | +| M8 | Arm64 | 9258.0 | 7617.1 | +1640.8 | +892336 | +| M9 | Arm64 | 2483238.8 | 911654.9 | +1571583.9 | +272191536 | diff --git a/docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/aggregator-out/trend.csv b/docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/aggregator-out/trend.csv new file mode 100644 index 00000000..3b7e6504 --- /dev/null +++ b/docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/aggregator-out/trend.csv @@ -0,0 +1,196 @@ +benchId,benchName,variant,machineSku,architecture,configuration,timestamp,iterations,repetition,meanNs,allocBytes,gen0,heapDeltaBytes,counter,counterLabel,status +M1,Mount_Leaf_NoCallback,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:40.3580700+00:00,5000,0,32151.50,3771824,1,1575176,0,,ok +M1,Mount_Leaf_NoCallback,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:40.5820197+00:00,5000,1,35969.04,3772088,1,1575544,0,,ok +M1,Mount_Leaf_NoCallback,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:40.7983133+00:00,5000,2,39812.24,3771824,1,1575320,0,,ok +M1,Mount_Leaf_NoCallback,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:41.0006428+00:00,5000,3,36663.78,3771824,1,1567360,0,,ok +M1,Mount_Leaf_NoCallback,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:41.1964562+00:00,5000,4,34379.20,3771824,1,1575584,0,,ok +M1,Mount_Leaf_NoCallback,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:41.8961715+00:00,5000,0,38777.76,6180504,2,1469824,0,,ok +M1,Mount_Leaf_NoCallback,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:42.1133523+00:00,5000,1,40834.94,6508760,2,2126088,0,,ok +M1,Mount_Leaf_NoCallback,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:42.3509870+00:00,5000,2,43781.68,6344552,2,1961880,0,,ok +M1,Mount_Leaf_NoCallback,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:42.5929299+00:00,5000,3,44035.24,6508760,2,2125824,0,,ok +M1,Mount_Leaf_NoCallback,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:42.8635782+00:00,5000,4,48138.66,6508496,2,2125464,0,,ok +M1,Mount_Leaf_NoCallback,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:43.5649936+00:00,5000,0,40012.10,6344712,2,1798016,0,,ok +M1,Mount_Leaf_NoCallback,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:43.8006103+00:00,5000,1,44147.62,6508496,2,2125728,0,,ok +M1,Mount_Leaf_NoCallback,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:44.0365663+00:00,5000,2,43215.22,6344816,2,1953656,0,,ok +M1,Mount_Leaf_NoCallback,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:44.2859510+00:00,5000,3,44891.62,6508496,2,2117320,0,,ok +M1,Mount_Leaf_NoCallback,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:44.5518534+00:00,5000,4,46836.00,6508336,2,2125824,0,,ok +M2,Mount_Leaf_OneCallback,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:45.2709203+00:00,5000,0,42487.04,13393016,3,2229576,0,,ok +M2,Mount_Leaf_OneCallback,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:45.5277095+00:00,5000,1,45475.06,13559024,4,1180744,0,,ok +M2,Mount_Leaf_OneCallback,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:45.8155153+00:00,5000,2,49854.88,13310520,3,2727600,0,,ok +M2,Mount_Leaf_OneCallback,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:46.1393333+00:00,5000,3,53637.92,13556752,3,2365416,0,,ok +M2,Mount_Leaf_OneCallback,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:46.5251244+00:00,5000,4,60927.08,13310520,3,1610640,0,,ok +M2,Mount_Leaf_OneCallback,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:48.3398948+00:00,5000,0,97852.98,17704680,5,7753384,0,,ok +M2,Mount_Leaf_OneCallback,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:49.0184240+00:00,5000,1,98677.04,18105936,4,12437152,0,,ok +M2,Mount_Leaf_OneCallback,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:49.9086538+00:00,5000,2,115190.22,17354552,3,12770400,0,,ok +M2,Mount_Leaf_OneCallback,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:50.8935870+00:00,5000,3,120832.74,21083392,3,13490664,0,,ok +M2,Mount_Leaf_OneCallback,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:52.0212791+00:00,5000,4,128839.04,17339424,3,11154136,0,,ok +M2,Mount_Leaf_OneCallback,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:55.2541614+00:00,5000,0,102644.52,24965760,2,21867576,0,,ok +M2,Mount_Leaf_OneCallback,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:56.4768927+00:00,5000,1,95088.74,17246872,2,14148696,0,,ok +M2,Mount_Leaf_OneCallback,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:57.8086539+00:00,5000,2,97178.68,15134736,2,12036432,0,,ok +M2,Mount_Leaf_OneCallback,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:17:59.1686318+00:00,5000,3,88281.98,19776560,2,16741536,0,,ok +M2,Mount_Leaf_OneCallback,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:18:00.7464136+00:00,5000,4,108946.88,15059256,2,11272416,0,,ok +M3,Mount_Leaf_ThreeCallbacks,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:18:06.8736489+00:00,5000,0,337017.70,25848800,7,-5072272,0,,ok +M3,Mount_Leaf_ThreeCallbacks,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:18:10.1546792+00:00,5000,1,376464.38,32666704,7,8503104,0,,ok +M3,Mount_Leaf_ThreeCallbacks,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:18:13.7044674+00:00,5000,2,427760.14,27160328,7,3291048,0,,ok +M3,Mount_Leaf_ThreeCallbacks,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:18:17.4822442+00:00,5000,3,467421.14,31092832,7,7103560,0,,ok +M3,Mount_Leaf_ThreeCallbacks,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:18:21.4218603+00:00,5000,4,502284.12,27686016,7,3507024,0,,ok +M3,Mount_Leaf_ThreeCallbacks,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:18:58.2889566+00:00,5000,0,273926.26,40296920,8,22023624,0,,ok +M3,Mount_Leaf_ThreeCallbacks,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:19:00.1849549+00:00,5000,1,318727.10,40289712,8,21120888,0,,ok +M3,Mount_Leaf_ThreeCallbacks,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:19:02.4696295+00:00,5000,2,373382.38,40295368,7,23766512,0,,ok +M3,Mount_Leaf_ThreeCallbacks,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:19:05.1415219+00:00,5000,3,436883.72,40206584,7,24393504,0,,ok +M3,Mount_Leaf_ThreeCallbacks,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:19:08.3275321+00:00,5000,4,489335.96,46586944,7,28789576,0,,ok +M3,Mount_Leaf_ThreeCallbacks,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:19:16.7246302+00:00,5000,0,271814.04,45547616,8,28539488,0,,ok +M3,Mount_Leaf_ThreeCallbacks,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:19:18.5964936+00:00,5000,1,313550.04,41591088,7,24163992,0,,ok +M3,Mount_Leaf_ThreeCallbacks,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:19:20.9961150+00:00,5000,2,388903.52,40281800,7,21627960,0,,ok +M3,Mount_Leaf_ThreeCallbacks,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:19:23.9010113+00:00,5000,3,451487.42,40289440,7,23613304,0,,ok +M3,Mount_Leaf_ThreeCallbacks,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:19:27.2418802+00:00,5000,4,527945.80,45539264,7,27732648,0,,ok +M4,Dispatch_Switch_Cold,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:19:29.8344000+00:00,5000,0,77748.78,4412192,0,4435744,0,,ok +M4,Dispatch_Switch_Cold,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:19:31.1691669+00:00,5000,1,68956.56,5723016,0,5746496,0,,ok +M4,Dispatch_Switch_Cold,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:19:32.5074061+00:00,5000,2,74814.22,4412192,0,4435744,0,,ok +M4,Dispatch_Switch_Cold,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:19:33.9242265+00:00,5000,3,81855.12,4412192,0,4440856,0,,ok +M4,Dispatch_Switch_Cold,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:19:35.3262430+00:00,5000,4,78757.86,4412192,0,4440856,0,,ok +M4,Dispatch_Switch_Cold,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:19:39.7373343+00:00,5000,0,142326.30,9345136,1,6673096,0,,ok +M4,Dispatch_Switch_Cold,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:19:41.3747753+00:00,5000,1,141058.56,9418992,1,6779096,0,,ok +M4,Dispatch_Switch_Cold,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:19:43.0104999+00:00,5000,2,146819.16,15940112,1,13285976,0,,ok +M4,Dispatch_Switch_Cold,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:19:44.7451710+00:00,5000,3,143643.42,9386200,1,6731888,0,,ok +M4,Dispatch_Switch_Cold,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:19:46.5072136+00:00,5000,4,148170.98,9451760,1,6826328,0,,ok +M4,Dispatch_Switch_Cold,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:19:57.8922091+00:00,5000,0,117982.04,9414400,5,-4739088,0,,ok +M4,Dispatch_Switch_Cold,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:19:58.7137935+00:00,5000,1,141670.64,9439592,7,1606336,0,,ok +M4,Dispatch_Switch_Cold,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:19:59.5428051+00:00,5000,2,135840.18,10692416,5,2897736,0,,ok +M4,Dispatch_Switch_Cold,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:00.4152066+00:00,5000,3,141185.58,9420568,5,2484800,0,,ok +M4,Dispatch_Switch_Cold,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:01.4080212+00:00,5000,4,158338.88,9568320,5,2635576,0,,ok +M5,Dispatch_Switch_Warm,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:02.6703927+00:00,5000,0,24419.66,4412192,0,4440680,0,,ok +M5,Dispatch_Switch_Warm,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:02.8981990+00:00,5000,1,31717.10,4412192,0,4435672,0,,ok +M5,Dispatch_Switch_Warm,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:03.1671618+00:00,5000,2,34852.84,4412192,0,4440632,0,,ok +M5,Dispatch_Switch_Warm,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:03.4596227+00:00,5000,3,40245.72,4412192,0,4440632,0,,ok +M5,Dispatch_Switch_Warm,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:03.7454719+00:00,5000,4,39314.86,5723016,0,5751456,0,,ok +M5,Dispatch_Switch_Warm,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:06.0393764+00:00,5000,0,127607.40,9427624,6,2049824,0,,ok +M5,Dispatch_Switch_Warm,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:06.8109474+00:00,5000,1,129151.46,14666168,5,2677008,0,,ok +M5,Dispatch_Switch_Warm,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:07.8233133+00:00,5000,2,172683.58,9397840,6,1592784,0,,ok +M5,Dispatch_Switch_Warm,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:08.8895229+00:00,5000,3,176676.08,10759352,7,1595608,0,,ok +M5,Dispatch_Switch_Warm,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:09.9900269+00:00,5000,4,181859.54,9432512,7,1608320,0,,ok +M5,Dispatch_Switch_Warm,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:12.7582619+00:00,5000,0,99623.60,9441152,6,1796752,0,,ok +M5,Dispatch_Switch_Warm,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:13.4074958+00:00,5000,1,113605.42,9419632,6,1712896,0,,ok +M5,Dispatch_Switch_Warm,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:14.1830911+00:00,5000,2,132107.40,10694144,7,1604584,0,,ok +M5,Dispatch_Switch_Warm,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:15.1375090+00:00,5000,3,163494.56,9712272,7,1529800,0,,ok +M5,Dispatch_Switch_Warm,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:16.1381285+00:00,5000,4,165368.76,9440944,7,1355328,0,,ok +M6,Dispatch_ExternalType,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:17.5306320+00:00,5000,0,43845.38,3607192,0,3633008,0,,ok +M6,Dispatch_ExternalType,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:17.8414185+00:00,5000,1,42679.76,3607192,0,3627136,0,,ok +M6,Dispatch_ExternalType,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:18.1720785+00:00,5000,2,43813.00,3607192,0,3627120,0,,ok +M6,Dispatch_ExternalType,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:18.5102632+00:00,5000,3,43303.06,3607192,0,3627136,0,,ok +M6,Dispatch_ExternalType,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:18.8470611+00:00,5000,4,41857.00,4918016,0,4937864,0,,ok +M6,Dispatch_ExternalType,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:19.9359443+00:00,5000,0,53808.08,4175088,3,812440,0,,ok +M6,Dispatch_ExternalType,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:20.2640258+00:00,5000,1,58002.20,4183128,3,814776,0,,ok +M6,Dispatch_ExternalType,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:20.5851700+00:00,5000,2,56925.74,4182536,3,820288,0,,ok +M6,Dispatch_ExternalType,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:20.9191975+00:00,5000,3,57552.14,4182536,3,820448,0,,ok +M6,Dispatch_ExternalType,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:21.3257112+00:00,5000,4,70020.06,4182536,3,820432,0,,ok +M6,Dispatch_ExternalType,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:22.1660725+00:00,5000,0,46315.78,4172168,2,806488,0,,ok +M6,Dispatch_ExternalType,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:22.5066629+00:00,5000,1,61365.38,4175088,3,812176,0,,ok +M6,Dispatch_ExternalType,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:22.8287921+00:00,5000,2,54427.36,4175088,3,812168,0,,ok +M6,Dispatch_ExternalType,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:23.1601622+00:00,5000,3,54952.52,5493920,2,2073816,0,,ok +M6,Dispatch_ExternalType,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:23.5392502+00:00,5000,4,61256.32,4175088,3,812136,0,,ok +M7,Update_NoChange,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:49.0889535+00:00,5000,0,1705280.80,122599664,30,4152456,0,,ok +M7,Update_NoChange,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:20:57.5290605+00:00,5000,1,1680497.70,122599664,30,4152456,0,,ok +M7,Update_NoChange,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:06.5413242+00:00,5000,2,1792833.90,122599664,30,4152456,0,,ok +M7,Update_NoChange,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:15.2893971+00:00,5000,3,1739612.60,122599664,30,4152456,0,,ok +M7,Update_NoChange,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:24.1854147+00:00,5000,4,1767151.40,122599664,30,4160680,0,,ok +M7,Update_NoChange,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:24.9142248+00:00,5000,0,22743.86,996032,0,1011528,0,,ok +M7,Update_NoChange,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:25.0837050+00:00,5000,1,24106.50,996032,0,1011528,0,,ok +M7,Update_NoChange,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:25.2413510+00:00,5000,2,23225.66,996032,0,1011528,0,,ok +M7,Update_NoChange,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:25.3933062+00:00,5000,3,21739.86,996032,0,1011528,0,,ok +M7,Update_NoChange,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:25.5306634+00:00,5000,4,18325.04,996032,0,1011528,0,,ok +M7,Update_NoChange,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:26.0155574+00:00,5000,0,21054.62,996032,0,1011528,0,,ok +M7,Update_NoChange,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:26.1751691+00:00,5000,1,22862.00,996032,0,1011528,0,,ok +M7,Update_NoChange,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:26.3204663+00:00,5000,2,20373.38,996032,0,1011528,0,,ok +M7,Update_NoChange,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:26.4790921+00:00,5000,3,23252.18,996032,0,1011528,0,,ok +M7,Update_NoChange,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:26.6340685+00:00,5000,4,21752.14,2306856,0,2322216,0,,ok +M8,Update_OneLeafChanged,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:26.9760736+00:00,5000,0,7879.58,915536,0,929352,0,,ok +M8,Update_OneLeafChanged,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:27.0506522+00:00,5000,1,7654.38,915536,0,929232,0,,ok +M8,Update_OneLeafChanged,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:27.1272434+00:00,5000,2,7827.46,915536,0,929232,0,,ok +M8,Update_OneLeafChanged,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:27.2018391+00:00,5000,3,7363.42,915536,0,929232,0,,ok +M8,Update_OneLeafChanged,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:27.2794199+00:00,5000,4,7360.72,915536,0,929232,0,,ok +M8,Update_OneLeafChanged,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:27.6208161+00:00,5000,0,11558.82,1807872,0,1825768,0,,ok +M8,Update_OneLeafChanged,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:27.7078539+00:00,5000,1,9811.84,1807872,0,1825624,0,,ok +M8,Update_OneLeafChanged,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:27.7920869+00:00,5000,2,8414.10,1807872,0,1825704,0,,ok +M8,Update_OneLeafChanged,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:27.8787673+00:00,5000,3,9238.38,1807872,0,1825704,0,,ok +M8,Update_OneLeafChanged,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:27.9658710+00:00,5000,4,8983.84,1807872,0,1825704,0,,ok +M8,Update_OneLeafChanged,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:28.3076386+00:00,5000,0,8895.10,1807872,0,1825704,0,,ok +M8,Update_OneLeafChanged,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:28.4054536+00:00,5000,1,10005.18,1807872,0,1825704,0,,ok +M8,Update_OneLeafChanged,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:28.4910962+00:00,5000,2,9258.18,1807872,0,1825624,0,,ok +M8,Update_OneLeafChanged,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:28.5743037+00:00,5000,3,8901.86,1807872,0,1825704,0,,ok +M8,Update_OneLeafChanged,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:28.6637158+00:00,5000,4,9229.44,1807872,0,1825704,0,,ok +M9,Update_AllChanged,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:35.2450629+00:00,2000,0,932325.20,96678016,22,3166616,0,,ok +M9,Update_AllChanged,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:37.0797120+00:00,2000,1,897738.70,96678016,22,3183376,0,,ok +M9,Update_AllChanged,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:38.8915531+00:00,2000,2,900973.65,96678016,22,3166616,0,,ok +M9,Update_AllChanged,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:40.7157459+00:00,2000,3,905227.25,96636952,22,3084432,0,,ok +M9,Update_AllChanged,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:42.5741821+00:00,2000,4,922009.90,96678016,22,3158392,0,,ok +M9,Update_AllChanged,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:21:59.9305830+00:00,2000,0,3153542.75,368894200,87,4030688,0,,ok +M9,Update_AllChanged,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:06.1853672+00:00,2000,1,3113011.10,368976224,87,4194952,0,,ok +M9,Update_AllChanged,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:12.3763199+00:00,2000,2,3082545.30,368812072,87,3866480,0,,ok +M9,Update_AllChanged,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:18.5444488+00:00,2000,3,3070901.70,368894200,87,4030688,0,,ok +M9,Update_AllChanged,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:24.7542797+00:00,2000,4,3092019.95,368812072,87,3866480,0,,ok +M9,Update_AllChanged,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:34.3452027+00:00,2000,0,1575567.25,368812072,87,3866320,0,,ok +M9,Update_AllChanged,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:37.5376466+00:00,2000,1,1588456.25,369058144,87,4351048,0,,ok +M9,Update_AllChanged,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:43.5981675+00:00,2000,2,3023963.10,368812072,87,3866480,0,,ok +M9,Update_AllChanged,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:49.8987228+00:00,2000,3,3137302.05,368812072,87,3858256,0,,ok +M9,Update_AllChanged,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:56.1126722+00:00,2000,4,3090905.35,368812336,87,3866744,0,,ok +M10,EventHandlerState_Alloc,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:56.8850820+00:00,1000,0,34520.90,2958312,0,2977344,0,,ok +M10,EventHandlerState_Alloc,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:56.9517087+00:00,1000,1,31895.70,2958312,0,2968752,0,,ok +M10,EventHandlerState_Alloc,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:56.9959240+00:00,1000,2,33678.40,2958312,0,2977320,0,,ok +M10,EventHandlerState_Alloc,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:57.0420226+00:00,1000,3,33814.00,2958312,0,2977320,0,,ok +M10,EventHandlerState_Alloc,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:57.0899411+00:00,1000,4,33838.60,2958312,0,2977320,0,,ok +M10,EventHandlerState_Alloc,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:57.3176695+00:00,1000,0,41999.20,3575080,0,3593432,0,,ok +M10,EventHandlerState_Alloc,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:57.3808777+00:00,1000,1,40383.60,3534016,0,3552376,0,,ok +M10,EventHandlerState_Alloc,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:57.4499007+00:00,1000,2,44279.30,3575080,0,3584928,0,,ok +M10,EventHandlerState_Alloc,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:57.5227658+00:00,1000,3,49239.60,3534016,0,3552416,0,,ok +M10,EventHandlerState_Alloc,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:57.5950310+00:00,1000,4,47422.00,3575080,0,3593432,0,,ok +M10,EventHandlerState_Alloc,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:57.8415351+00:00,1000,0,41096.20,3329008,0,3338880,0,,ok +M10,EventHandlerState_Alloc,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:57.9017719+00:00,1000,1,45718.40,3779776,0,3798064,0,,ok +M10,EventHandlerState_Alloc,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:57.9638411+00:00,1000,2,43408.00,3329008,0,3347384,0,,ok +M10,EventHandlerState_Alloc,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:58.0223481+00:00,1000,3,41781.80,3287944,0,3306368,0,,ok +M10,EventHandlerState_Alloc,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:58.0849337+00:00,1000,4,45245.60,3329008,0,3347424,0,,ok +M11,ModifierEHS_Frequency,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:58.1644158+00:00,1000,0,83.10,40,0,8224,0,,ok +M11,ModifierEHS_Frequency,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:58.1662856+00:00,1000,1,23.40,40,0,8224,0,,ok +M11,ModifierEHS_Frequency,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:58.1682302+00:00,1000,2,22.10,40,0,8224,0,,ok +M11,ModifierEHS_Frequency,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:58.1703016+00:00,1000,3,20.80,40,0,8224,0,,ok +M11,ModifierEHS_Frequency,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:58.1721363+00:00,1000,4,20.10,40,0,8224,0,,ok +M11,ModifierEHS_Frequency,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:58.3372503+00:00,1000,0,38087.30,1619056,0,1634024,-1,ModifierEHSAllocations,ok +M11,ModifierEHS_Frequency,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:58.3853913+00:00,1000,1,36577.30,1610840,0,1620128,-1,ModifierEHSAllocations,ok +M11,ModifierEHS_Frequency,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:58.4357609+00:00,1000,2,38521.30,1610840,0,1628496,-1,ModifierEHSAllocations,ok +M11,ModifierEHS_Frequency,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:58.4873211+00:00,1000,3,37825.30,1627248,0,1644952,-1,ModifierEHSAllocations,ok +M11,ModifierEHS_Frequency,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:58.5426192+00:00,1000,4,42017.40,2102672,0,2117312,-1,ModifierEHSAllocations,ok +M11,ModifierEHS_Frequency,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:59.1779689+00:00,1000,0,32680.00,1538200,0,1554464,-1,ModifierEHSAllocations,ok +M11,ModifierEHS_Frequency,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:59.2293340+00:00,1000,1,33282.80,1565768,0,1579104,-1,ModifierEHSAllocations,ok +M11,ModifierEHS_Frequency,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:59.2808595+00:00,1000,2,32607.60,1538464,0,1554488,-1,ModifierEHSAllocations,ok +M11,ModifierEHS_Frequency,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:59.3365090+00:00,1000,3,36015.20,2024808,0,2038024,-1,ModifierEHSAllocations,ok +M11,ModifierEHS_Frequency,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:22:59.3950159+00:00,1000,4,36611.60,1538200,0,1554512,-1,ModifierEHSAllocations,ok +M12,Pool_Rent_HotPath,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.0445350+00:00,1000,0,25423.20,727272,0,737344,0,,ok +M12,Pool_Rent_HotPath,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.0795872+00:00,1000,1,25283.90,727272,0,739944,0,,ok +M12,Pool_Rent_HotPath,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.1153578+00:00,1000,2,26145.60,727272,0,739944,0,,ok +M12,Pool_Rent_HotPath,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.1508259+00:00,1000,3,25656.70,891216,0,904032,0,,ok +M12,Pool_Rent_HotPath,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.1871539+00:00,1000,4,26527.60,727536,0,740128,0,,ok +M12,Pool_Rent_HotPath,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.3585454+00:00,1000,0,33367.50,1207720,0,1225232,0,,ok +M12,Pool_Rent_HotPath,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.3976674+00:00,1000,1,32213.30,1207720,0,1225232,0,,ok +M12,Pool_Rent_HotPath,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.4382482+00:00,1000,2,33870.50,1207720,0,1225320,0,,ok +M12,Pool_Rent_HotPath,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.4798594+00:00,1000,3,33695.00,1535608,0,1553144,0,,ok +M12,Pool_Rent_HotPath,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.5220784+00:00,1000,4,33080.60,1371664,0,1389248,0,,ok +M12,Pool_Rent_HotPath,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.6510066+00:00,1000,0,33435.10,1207984,0,1225288,0,,ok +M12,Pool_Rent_HotPath,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.6893664+00:00,1000,1,32032.10,1207720,0,1225320,0,,ok +M12,Pool_Rent_HotPath,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.7296304+00:00,1000,2,33033.80,1207720,0,1217152,0,,ok +M12,Pool_Rent_HotPath,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.7698518+00:00,1000,3,34080.90,1207720,0,1225272,0,,ok +M12,Pool_Rent_HotPath,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.8324973+00:00,1000,4,40143.10,1535608,0,1553144,0,,ok +M13,Setters_Suppression_Scope,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.8554312+00:00,1000,0,62.70,24040,0,25096,0,,ok +M13,Setters_Suppression_Scope,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.8583401+00:00,1000,1,20.80,24040,0,24672,0,,ok +M13,Setters_Suppression_Scope,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.8601287+00:00,1000,2,19.70,24040,0,24672,0,,ok +M13,Setters_Suppression_Scope,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.8616758+00:00,1000,3,53.50,24040,0,24672,0,,ok +M13,Setters_Suppression_Scope,Direct,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.8646573+00:00,1000,4,20.70,24040,0,24672,0,,ok +M13,Setters_Suppression_Scope,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.8747608+00:00,1000,0,115.10,29320,0,45104,0,OnIsOnChangedFireCount,ok +M13,Setters_Suppression_Scope,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.8765320+00:00,1000,1,99.30,29320,0,41096,0,OnIsOnChangedFireCount,ok +M13,Setters_Suppression_Scope,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.8781724+00:00,1000,2,92.30,29584,0,45104,0,OnIsOnChangedFireCount,ok +M13,Setters_Suppression_Scope,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.8800078+00:00,1000,3,123.20,29320,0,36928,0,OnIsOnChangedFireCount,ok +M13,Setters_Suppression_Scope,ReactorToday,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.8827153+00:00,1000,4,103.90,29320,0,32896,0,OnIsOnChangedFireCount,ok +M13,Setters_Suppression_Scope,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.8913809+00:00,1000,0,128.70,29320,0,45128,0,OnIsOnChangedFireCount,ok +M13,Setters_Suppression_Scope,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.8938479+00:00,1000,1,92.50,29320,0,41096,0,OnIsOnChangedFireCount,ok +M13,Setters_Suppression_Scope,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.8956291+00:00,1000,2,80.50,29320,0,32896,0,OnIsOnChangedFireCount,ok +M13,Setters_Suppression_Scope,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.8979304+00:00,1000,3,700.20,29320,0,32896,0,OnIsOnChangedFireCount,ok +M13,Setters_Suppression_Scope,Reactor,LAPTOP-4MEP83VI,Arm64,Release,2026-05-30T06:23:00.8995586+00:00,1000,4,100.90,29320,0,45104,0,OnIsOnChangedFireCount,ok diff --git a/docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/analyze.py b/docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/analyze.py new file mode 100644 index 00000000..acb15431 --- /dev/null +++ b/docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/analyze.py @@ -0,0 +1,103 @@ +#!/usr/bin/env python3 +"""Spec-047 §15.6 comparison: post-Phase-4 capture vs 2026-05-25 ARM64 baseline. + +Computes per-render mean (allocBytes/iterations) and per-op meanNs for each +(benchId, variant), averaged across reps. Maps baseline 'ReactorV2' and current +'Reactor' to a common 'Reactor' label (same code lineage — the post-047 V1 path). +""" +import json, glob, sys, statistics, os + +BASE = "docs/specs/047/baseline-results/LAPTOP-4MEP83VI/2026-05-25-arm64" +NEW = "perf-capture-2026-05-29-arm64" + +def load(files): + rows = [] + for f in files: + with open(f) as fh: + for line in fh: + line = line.strip() + if line: + rows.append(json.loads(line)) + return rows + +def norm_variant(v): + return "Reactor" if v in ("Reactor", "ReactorV2") else v + +def agg(rows): + # key (bench, variant) -> dict with per-render alloc list, ns list + g = {} + for r in rows: + if r.get("status") != "ok": + continue + b = r["benchId"]; v = norm_variant(r["variant"]); it = r["iterations"] + key = (b, v) + d = g.setdefault(key, {"alloc": [], "ns": [], "iters": it}) + d["alloc"].append(r["allocBytes"] / it) # per-render bytes + d["ns"].append(r["meanNs"]) # per-op ns + out = {} + for key, d in g.items(): + out[key] = { + "alloc": statistics.mean(d["alloc"]), + "ns": statistics.mean(d["ns"]), + "iters": d["iters"], + "n": len(d["alloc"]), + } + return out + +base = agg(load(sorted(glob.glob(f"{BASE}/perfbench-controlmodel*.jsonl")))) +new = agg(load(sorted(glob.glob(f"{NEW}/perfbench-controlmodel*.jsonl")))) + +benches = ["M1","M2","M3","M4","M5","M6","M7","M8","M9","M10","M11","M12","M13"] + +def pct(new_v, old_v): + if old_v == 0: return "n/a" + return f"{(new_v-old_v)/old_v*100:+.1f}%" + +def g(tbl, b, v, field): + r = tbl.get((b, v)) + return r[field] if r else None + +print("# Spec-047 §15.6 — Post-Phase-4 capture vs 2026-05-25 ARM64 baseline (LAPTOP-4MEP83VI)\n") +print("Per-render allocated bytes (allocBytes / iterations), mean across 5 reps.\n") + +# ---- ALLOC table ---- +print("## Per-render ALLOC bytes\n") +print("| Bench | Direct (new) | Direct (base) | Reactor (new) | Reactor=V2 (base) | new vs base-V2 | Today (base) | new-Reactor vs base-Today |") +print("|---|---:|---:|---:|---:|---:|---:|---:|") +for b in benches: + dn = g(new,b,"Direct","alloc"); db = g(base,b,"Direct","alloc") + rn = g(new,b,"Reactor","alloc"); rb = g(base,b,"Reactor","alloc") + tb = g(base,b,"ReactorToday","alloc") + def f(x): return f"{x:,.0f}" if x is not None else "-" + vV2 = pct(rn, rb) if (rn is not None and rb) else "-" + vTd = pct(rn, tb) if (rn is not None and tb) else "-" + print(f"| {b} | {f(dn)} | {f(db)} | {f(rn)} | {f(rb)} | {vV2} | {f(tb)} | {vTd} |") + +# ---- NS table ---- +print("\n## Per-op mean NS\n") +print("| Bench | Direct (new) | Reactor (new) | Reactor=V2 (base) | new vs base-V2 | Today (base) | new-Reactor vs base-Today |") +print("|---|---:|---:|---:|---:|---:|---:|") +for b in benches: + dn = g(new,b,"Direct","ns") + rn = g(new,b,"Reactor","ns"); rb = g(base,b,"Reactor","ns") + tb = g(base,b,"ReactorToday","ns") + def f(x): return f"{x:,.0f}" if x is not None else "-" + vV2 = pct(rn, rb) if (rn is not None and rb) else "-" + vTd = pct(rn, tb) if (rn is not None and tb) else "-" + print(f"| {b} | {f(dn)} | {f(rn)} | {f(rb)} | {vV2} | {f(tb)} | {vTd} |") + +# ---- Byte gate ---- +print("\n## §11.6 byte-gate (per-render Reactor-new vs target)\n") +gates = {"M1":407,"M2":1520,"M3":19200} +print("| Bench | Target | Reactor (new) per-render | Pass? |") +print("|---|---:|---:|:---:|") +for b,t in gates.items(): + rn = g(new,b,"Reactor","alloc") + ok = "✅" if (rn is not None and rn <= t) else "❌" + print(f"| {b} | ≤{t:,} | {rn:,.0f} | {ok} |" if rn is not None else f"| {b} | ≤{t:,} | - | - |") + +# ---- env / sanity ---- +print("\n## Capture coverage\n") +for b in benches: + have = [v for v in ("Direct","ReactorToday","Reactor") if (b,v) in new] + print(f"- {b}: {', '.join(have) if have else 'MISSING'} (iters={g(new,b,'Reactor','iters')})") diff --git a/docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/perfbench-controlmodel-m1-m8.jsonl b/docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/perfbench-controlmodel-m1-m8.jsonl new file mode 100644 index 00000000..508a3cbf --- /dev/null +++ b/docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/perfbench-controlmodel-m1-m8.jsonl @@ -0,0 +1,120 @@ +{"benchId":"M1","benchName":"Mount_Leaf_NoCallback","variant":"Direct","iterations":5000,"repetition":0,"totalMs":160.7575,"meanNs":32151.5,"allocBytes":3771824,"gen0":1,"gen1":1,"gen2":1,"heapDeltaBytes":1575176,"counter":0,"counterLabel":null,"status":"ok","note":null,"machineSku":"LAPTOP-4MEP83VI","cpu":"ARMv8 (64-bit) Family 8 Model 1 Revision 201, Qualcomm Technologies Inc","osBuild":"Microsoft Windows NT 10.0.26200.0","dotnetVersion":".NET 10.0.8","architecture":"Arm64","configuration":"Release","powerState":"unknown","powerPlan":"unknown","timestamp":"2026-05-30T06:17:40.35807+00:00"} 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Inc","osBuild":"Microsoft Windows NT 10.0.26200.0","dotnetVersion":".NET 10.0.8","architecture":"Arm64","configuration":"Release","powerState":"unknown","powerPlan":"unknown","timestamp":"2026-05-30T06:22:49.8987228+00:00"} +{"benchId":"M9","benchName":"Update_AllChanged","variant":"Reactor","iterations":2000,"repetition":4,"totalMs":6181.8107,"meanNs":3090905.35,"allocBytes":368812336,"gen0":87,"gen1":0,"gen2":0,"heapDeltaBytes":3866744,"counter":0,"counterLabel":null,"status":"ok","note":null,"machineSku":"LAPTOP-4MEP83VI","cpu":"ARMv8 (64-bit) Family 8 Model 1 Revision 201, Qualcomm Technologies Inc","osBuild":"Microsoft Windows NT 10.0.26200.0","dotnetVersion":".NET 10.0.8","architecture":"Arm64","configuration":"Release","powerState":"unknown","powerPlan":"unknown","timestamp":"2026-05-30T06:22:56.1126722+00:00"} From fcdc94b75b0a3433526699fb59e6640344ea79fd Mon Sep 17 00:00:00 2001 From: Chris Anderson Date: Fri, 29 May 2026 23:46:10 -0700 Subject: [PATCH 2/2] =?UTF-8?q?spec-047:=20record=20=C2=A74.9/=C2=A711.6?= =?UTF-8?q?=20measured=20results=20from=20the=20ARM64=20capture=20(PR=20#4?= =?UTF-8?q?65)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Updates the spec body + both trackers to reflect the indicative LAPTOP-4MEP83VI capture now that the deterministic allocation axis is measured: - §4.4/§11.6 byte gates MEASURED: M3 PASS; M1 (3.2×) + M2 (2.4×) FAIL. - §15.6 "M1–M3 alloc ≤ Today": M2/M3 PASS, M1 +20.3% FAIL; M12 +17% regressed. - KD-3 trigger CONFIRMED (M1 over budget) — fold warranted + investigate the bucketing regression. - Gate stays OPEN: timing axis throttled (no §15.5 isolation), macro suite unrunnable (projects deleted in Phase 4); needs an isolated re-capture + the M1/M12 alloc fix. Co-Authored-By: Claude Opus 4.8 (1M context) --- docs/specs/047-extensible-control-model.md | 18 ++++-- ...extensible-control-model-implementation.md | 15 +++-- ...ble-control-model-phase4-implementation.md | 60 ++++++++++++++++--- 3 files changed, 78 insertions(+), 15 deletions(-) diff --git a/docs/specs/047-extensible-control-model.md b/docs/specs/047-extensible-control-model.md index c753f66a..f2ef7074 100644 --- a/docs/specs/047-extensible-control-model.md +++ b/docs/specs/047-extensible-control-model.md @@ -1530,7 +1530,7 @@ ARM64 stable-AC re-capture on `LAPTOP-4MEP83VI` remains deferred for the §14 ra - **New regressions vs close-out:** M8 +21.8% (+2.9pp — Lazy*Stack base-derived registration's added is-check in the Update path), M12 +30.7% (+12.2pp — Cloud-PC volatile; M12 has trended ±15pp across the last three captures and should be confirmed on stable AC). - **Net headline:** no bench exceeds the §13 Q1 reopen threshold. The structural wins (dispatch consolidation, single `IItemsBinderStrategy` arm) are in place; the absolute Cloud-PC numbers track the close-out baseline. -**ARM64 stable-AC ratification gate** — **still pending; first capture attempt was inconclusive.** An ARM64-native 3×5 capture on `LAPTOP-4MEP83VI` (the Phase 0/2 baseline machine) landed under [`docs/specs/047/phase3-results/LAPTOP-4MEP83VI/2026-05-28-phase3-completion-3x5-stableac/`](047/phase3-results/LAPTOP-4MEP83VI/2026-05-28-phase3-completion-3x5-stableac/README.md) but **does not ratify the gate**: the fixed variant-ordering run drifted under sustained load (suspected thermal throttling — `ReactorDescriptors` always runs last and so against the hottest core), inflating long-bench deltas (M2 +23.4%, M3 +175.3%, M12 +44.2% vs Today). A controlled **order-swap re-run** (Descriptors first/cold) proves the contamination: M2's Descriptors-vs-Today delta flips from +23.4% to −30.5% (a 54pp position swing), and Descriptors-vs-ReactorV2 collapses from +36.1% to +1.1% — i.e. no real M2 regression. The thermally-insensitive fast benches confirm descriptors ≈ hand-coded V1 (M1/M7/M8/M11/M13 within ±5% vs ReactorV2), and M1's order-robust +30% vs Today is the known V1-protocol-vs-legacy mount overhead, not descriptor-specific. **A thermally-clean ARM64 re-run** (randomized/interleaved variant order, cooldowns, and/or CPU-clock telemetry) is still required to close the gate; until then it remains pending with a named owner + date to be appended. See the capture README for the full drift evidence and reproduction steps. +**ARM64 stable-AC ratification gate** — **still pending; first capture attempt was inconclusive.** An ARM64-native 3×5 capture on `LAPTOP-4MEP83VI` (the Phase 0/2 baseline machine) landed under [`docs/specs/047/phase3-results/LAPTOP-4MEP83VI/2026-05-28-phase3-completion-3x5-stableac/`](047/phase3-results/LAPTOP-4MEP83VI/2026-05-28-phase3-completion-3x5-stableac/README.md) but **does not ratify the gate**: the fixed variant-ordering run drifted under sustained load (suspected thermal throttling — `ReactorDescriptors` always runs last and so against the hottest core), inflating long-bench deltas (M2 +23.4%, M3 +175.3%, M12 +44.2% vs Today). A controlled **order-swap re-run** (Descriptors first/cold) proves the contamination: M2's Descriptors-vs-Today delta flips from +23.4% to −30.5% (a 54pp position swing), and Descriptors-vs-ReactorV2 collapses from +36.1% to +1.1% — i.e. no real M2 regression. The thermally-insensitive fast benches confirm descriptors ≈ hand-coded V1 (M1/M7/M8/M11/M13 within ±5% vs ReactorV2), and M1's order-robust +30% vs Today is the known V1-protocol-vs-legacy mount overhead, not descriptor-specific. **A thermally-clean ARM64 re-run** (randomized/interleaved variant order, cooldowns, and/or CPU-clock telemetry) is still required to close the gate; until then it remains pending with a named owner + date to be appended. See the capture README for the full drift evidence and reproduction steps. **Phase-4 update (PR #465):** a post-Phase-4 capture landed under [`docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/`](047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/RESULTS.md); it **still does not close the gate** (same gap — fixed ordering, no §15.5 isolation, so the timing axis is throttled and the macro suite is unrunnable post-Phase-4). Its value is the deterministic **allocation** axis: most benches held/improved vs the 2026-05-25 baseline (M9 −41%), but **M1 regressed +20%** (3.2× over its 407 B gate) and **M12 +17%** — so the M1 leaf-alloc work (KD-3 fold + bucketing-regression investigation) is now confirmed as required, ahead of the thermally-clean re-run. **Carry-forward known defects from Phase 1:** - **KD-3** — dispatch fast-path for the ported built-ins (M4 was +88.9% V1 vs Today at Phase 1; final advisory shows M4 −21.2% / M5 −24.3% at amortized scope — KD-3 has materially closed at the batch-11 registration set). @@ -1541,7 +1541,14 @@ ARM64 stable-AC re-capture on `LAPTOP-4MEP83VI` remains deferred for the §14 ra **Status: code-complete — migration closed; V1 is the unconditional production path.** The only outstanding items are baseline-machine-only (ARM64 `LAPTOP-4MEP83VI`): the stable-AC perf ratification and the §11.6 hard byte-gate -*measurement/enforcement*. See the close-out tracker +*measurement/enforcement*. An **indicative ARM64 capture has landed** (PR #465, +`047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/`): the deterministic +**allocation** axis is measured — M2/M3 meet the §15.6 "≤ Today" budget, **M1 +regressed +20%** (and M1/M2 miss the absolute 407/1,520 B gates; M3 passes), plus +an **M12 +17%** pool-reuse regression. The **timing** axis (no §15.5 isolation) +and the **macro suite** (its projects were deleted in Phase 4) remain unratified, +so the gate is **not yet closed** — it needs an isolated stable-AC re-capture and +the M1/M12 alloc fix. See the close-out tracker [`tasks/047-extensible-control-model-phase4-implementation.md`](tasks/047-extensible-control-model-phase4-implementation.md). - ✅ Delete the private switch. *(Done §4.5 — dispatch is V1 registry → @@ -1560,8 +1567,11 @@ path.** The only outstanding items are baseline-machine-only (ARM64 for no-callback / one-callback / three-callback; the stale `≤100 / ≤320 / ≤500` estimates predate the Phase-0 baseline capture). *(Code-complete: the bucketed `Element` base (§11.7, `ElementExtras`) ships and the target constants are - landed (`PerformanceBudgets.cs`); the gate **measurement/enforcement** is - ARM64-baseline-blocked — §4.4/§4.9 handoff.)* + landed (`PerformanceBudgets.cs`); the gate has now been **MEASURED** on + `LAPTOP-4MEP83VI` ARM64 (PR #465): **M1 1,289 B (FAIL, 3.2×), M2 3,687 B + (FAIL, 2.4×), M3 8,530 B (PASS)** per-render. The gates do **not** pass for + M1/M2 — enforcement stays open pending the M1 leaf-alloc fix + an isolated + re-capture. §4.4/§4.9 handoff.)* - ✅ Document the final author-facing surface in `docs/guide/`. *(Done §4.8.)* ### Future: source generation (deferred, no committed timeline) diff --git a/docs/specs/tasks/047-extensible-control-model-implementation.md b/docs/specs/tasks/047-extensible-control-model-implementation.md index b06803f3..12543fca 100644 --- a/docs/specs/tasks/047-extensible-control-model-implementation.md +++ b/docs/specs/tasks/047-extensible-control-model-implementation.md @@ -29,10 +29,17 @@ Derived from: `docs/specs/047-extensible-control-model.md` > `EventHandlerState` split into `ModifierEventHandlerState` + per-control > `ControlEventStateBox` (§4.3); the §11.7 bucketed `Element` base > (`ElementExtras`) + the §11.6 byte-gate target constants (§4.4); and the final -> author docs (§4.8). **Outstanding (baseline-machine-only, handed off):** the -> ARM64 stable-AC perf ratification (§4.9) and the §11.6 hard byte-gate -> *measurement/enforcement* (§4.4) — both blocked on `LAPTOP-4MEP83VI`. Full -> x64 validation green throughout (build / xunit 9128 / selftests). +> author docs (§4.8). **Outstanding (baseline-machine-only, partially landed):** +> the ARM64 stable-AC perf ratification (§4.9) and the §11.6 hard byte-gate +> *measurement/enforcement* (§4.4). An **indicative ARM64 capture landed on +> `LAPTOP-4MEP83VI`** (PR #465, `047/phase4-results/.../2026-05-29-arm64/`): the +> deterministic **allocation** axis is now measured — **M2/M3 meet the §15.6 +> "≤ Today" budget, but M1 regressed +20%** (and M1/M2 miss the absolute +> 407/1,520 B gates; M3 passes); **M12 +17%** also regressed. The **timing** axis +> and the **macro suite (L1–L14)** are still unratified (no §15.5 isolation; +> macro projects deleted in Phase 4), so a full sign-off + the M1/M12 alloc fix +> remain open. Full x64 correctness validation green throughout (build / xunit +> 9128 / selftests). > > Phase 0 below is *spec-process* work — audits, suite infrastructure, baseline > measurements, and decision criteria. It cleared its exit gate (PR #414) and diff --git a/docs/specs/tasks/047-extensible-control-model-phase4-implementation.md b/docs/specs/tasks/047-extensible-control-model-phase4-implementation.md index 67de95e3..38993b9f 100644 --- a/docs/specs/tasks/047-extensible-control-model-phase4-implementation.md +++ b/docs/specs/tasks/047-extensible-control-model-phase4-implementation.md @@ -756,10 +756,16 @@ bucketed base landing. per §11.6 (`Target = min(Direct + 100, ReactorToday × 0.4)` — i.e. the measured ≤407 / ≤1520 / ≤19200, **not** the stale §14 ≤100/≤320/≤500 estimates). *(Code-complete: the §11.6 TARGET constants are landed in - `src/Reactor/Core/PerformanceBudgets.cs` (407/1520/19200). The - merge-blocking ENFORCEMENT/MEASUREMENT is ARM64-baseline-blocked → deferred - to §4.9; box stays open until ratified on `LAPTOP-4MEP83VI`. Commit - `60f4a908`.)* + `src/Reactor/Core/PerformanceBudgets.cs` (407/1520/19200). **MEASURED** on + `LAPTOP-4MEP83VI` ARM64 (PR #465 — indicative capture 2026-05-29, + `docs/specs/047/phase4-results/.../2026-05-29-arm64/`): per-render alloc is + **M1 1,289 B (3.2× over 407 — FAIL)**, **M2 3,687 B (2.4× over 1,520 — + FAIL)**, **M3 8,530 B (≤19,200 — PASS)**. The gates are therefore NOT met + for M1/M2 — box stays open. Closing it needs the M1/M2 leaf-alloc + follow-up (the deferred KD-3 M1 binder-check fold + investigating the + **M1 +20% / M12 +17% alloc regressions** vs the pre-bucketing baseline) + and an isolated stable-AC re-capture to wire the merge-blocking + enforcement. Commit `60f4a908`.)* - [x] **Spec hygiene:** update spec §14 "Phase 4 — cleanup" to cite the measured §11.6 targets instead of the stale `≤100 / ≤320 / ≤500`, and fix the §15.6 "Phase 5 cleanup" reference to read "Phase 4" (this spec has no @@ -768,7 +774,13 @@ bucketed base landing. "Phase 5 cleanup" reference now reads "Phase 4 cleanup".)* - [ ] **Validation.** M1/M2/M3 pass the hard gates on the baseline machine; L4/L5 working-set within the §15.6 budgets; M7 (no-change update) ≤ Today. - *(ARM64-baseline-blocked — deferred to §4.9. In this x64 env the bucketing is + *(PARTIAL — alloc axis measured on `LAPTOP-4MEP83VI` ARM64 (PR #465): the + §15.6 "M1–M3 alloc ≤ Today" budget is met for **M2 (−5.1%)** and + **M3 (−6.0%)** but FAILS for **M1 (+20.3%)**; the absolute hard gates remain + unmet for M1/M2 (above). L4/L5 (working-set) and M7 (timing) are NOT + ratified — the macro projects were deleted in Phase 4 and the timing axis is + environment-throttled in the non-isolated capture. The original x64 + CORRECTNESS validation stands. In this x64 env the bucketing is validated for CORRECTNESS: build 0 err; xunit 9128/0; the full animation/transition/theme/context/attached/stagger/keyframe/scroll/ connected-animation/resource selftest families 0 fail.)* @@ -963,8 +975,24 @@ Source: spec §14 Phase 4 ("Document the final author-facing surface in Source: spec §15.6 / §15.7 Phase 4 row, Phase 1 deferrals 1.17 / 1.18 / 1.19, and the still-pending ARM64 stable-AC ratification gate (§14 Phase 3 finish). -> **🔴 STATUS: ENTIRELY ARM64-BASELINE-BLOCKED — HANDED OFF (not executable in -> the x64 dev environment).** Every bullet below is a *measurement/ratification* +> **🟡 STATUS: INDICATIVE ARM64 CAPTURE LANDED (alloc-only); FULL RATIFICATION +> STILL PENDING.** A post-Phase-4 micro capture (M1–M13) ran on the baseline box +> `LAPTOP-4MEP83VI` (ARM64-native, Release, .NET 10.0.8, reps=5, baseline-matched +> iters) and is committed under +> `docs/specs/047/phase4-results/LAPTOP-4MEP83VI/2026-05-29-arm64/` (PR #465). +> The **allocation axis is valid** (deterministic — `Direct` alloc matches the +> 2026-05-25 baseline byte-for-byte) and is ratified in the boxes below. The +> **timing axis is NOT valid**: §15.5 isolation (AC / High-Perf / DRR-off / +> foreground) was not enforced, so `Direct` ns inflated +60–140% vs baseline; and +> the §4.9-mandated randomized/interleaved ordering + CPU-clock telemetry is not +> wired. The **macro suite (L1–L14) is unrunnable** — its projects +> (`StressPerf.ReactorV2`, `BlankReactorV2`) were deleted in Phase 4. A full +> sign-off still needs an isolated stable-AC re-capture + the macro suite rebuilt +> against the single `Reactor` variant. **Headline alloc result:** most benches +> held/improved vs baseline (M9 −41%), but **M1 regressed +20%** (3.2× over its +> 407 B gate) and **M12 +17%** — confirming the KD-3 M1-over-budget trigger. +> +> Every bullet below is a *measurement/ratification* > on the Phase 0/2 baseline machine `LAPTOP-4MEP83VI` (ARM64-native, Release, > stable-AC) per the §15.5 runbook; results commit under > `docs/specs/047/phase4-results/LAPTOP-4MEP83VI/`. The boxes stay **unchecked** @@ -991,6 +1019,11 @@ and the still-pending ARM64 stable-AC ratification gate (§14 Phase 3 finish). defeat the thermal drift that made the prior attempt inconclusive. Commit under `docs/specs/047/phase4-results/LAPTOP-4MEP83VI/`. Must clear the §13 Q1 thresholds and the §15.6 budgets. + *(PARTIAL — PR #465 landed a `2026-05-29-arm64/` capture, but WITHOUT the + randomized/interleaved ordering + CPU-clock telemetry and WITHOUT §15.5 + stable-AC isolation, so it does NOT yet satisfy this box. The allocation + portion is valid and analyzed (`RESULTS.md`); the timing portion is + throttled and must be re-captured under isolation. Box stays open.)* - [ ] **1.17 — AOT publish + L13 / L14.** AOT publish the split-library scenario with `PublishTrimmed=true` + `IsAotCompatible=true`; zero new trim/AOT warnings. L13 (mixed-tree, ≥50% external-assembly element types ≤ +10% vs @@ -1003,11 +1036,24 @@ and the still-pending ARM64 stable-AC ratification gate (§14 Phase 3 finish). (M1–M3, must improve/equal), dispatch (M4–M6 ±10%), update (M7 ±5% / M8 ≤+10%), TTFF (L1–L3 ≤+5%), working set (L4 ≤+2% / L5 ≤+5%), FPS (L6–L8 p95 ≤105%), GC pauses (L9 ≤ baseline), heap stability (L11 ±10%). + *(PARTIAL — PR #465, alloc only. per-element alloc (M1–M3): **M2 −5.1%, + M3 −6.0% PASS**; **M1 +20.3% FAIL**. Dispatch (M4–M6) and update (M7/M8) + are TIMING classes → not ratifiable from the throttled capture. TTFF / + working-set / FPS / GC / heap (L-series) → macro suite unrunnable + post-Phase-4. Box stays open pending the isolated re-capture + the M1 + alloc fix.)* - [ ] Confirm KD-3 (dispatch fast-path for ported built-ins) stays closed at the full registration scope (advisory showed M4/M5 net negative — wins from a fatter handler table). Fold the M1 leading-`if` binder check into the pattern-switch `case` arm (the Phase 3-finish note flagged this as the Phase 4 perf-tuning item) if M1 is still above budget after §4.3 / §4.4. + *(TRIGGER NOW CONFIRMED — PR #465 measured **M1 at 1,289 B/render, +20.3% + over Today and 3.2× over the 407 B gate**, i.e. M1 IS still above budget + after §4.3/§4.4 (in fact it regressed). The M1 binder-check fold is + therefore warranted; additionally investigate why the §4.4 bucketing made + the leanest leaf HEAVIER (candidate sources: the added `Element.Extensions` + slot, the §4.3 EHS split, the `ReactorState.PendingEchoMatch` slot) and the + **M12 +17%** pool-reuse regression. Apply + re-measure under isolation.)* ## 4.10 Final close-out checklist