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Windows GPU TensorRT CI Pipeline

Fix misaligned addresses while reading tensor attributes from raw data buffers #10428

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Fix misaligned addresses while reading tensor attributes from raw data buffers

Fix misaligned addresses while reading tensor attributes from raw data buffers #10428

Re-run triggered February 14, 2026 00:39
@yuslepukhinyuslepukhin
#27312
n-v-k:main
Status Success
Total duration 3h 37m 32s
Artifacts 1

windows_tensorrt.yml

on: pull_request
Windows GPU TensorRT CI Pipeline
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Windows GPU TensorRT CI Pipeline
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6 warnings
Windows GPU TensorRT CI Pipeline: onnxruntime/core/mlas/lib/amd64/QgemmU8X8KernelAvx2.asm#L1234
epilog offset from end of function exceeds 4095
Windows GPU TensorRT CI Pipeline: onnxruntime/core/mlas/lib/amd64/QgemmU8X8KernelAvx2.asm#L1227
epilog offset from end of function exceeds 4095
Windows GPU TensorRT CI Pipeline: onnxruntime/core/mlas/lib/amd64/QgemmU8X8KernelAvx2.asm#L1220
epilog offset from end of function exceeds 4095
Windows GPU TensorRT CI Pipeline: onnxruntime/core/mlas/lib/amd64/QgemmU8X8KernelAvx2.asm#L1213
epilog offset from end of function exceeds 4095
Windows GPU TensorRT CI Pipeline: onnxruntime/core/mlas/lib/amd64/QgemmU8X8KernelAvx2.asm#L1206
epilog offset from end of function exceeds 4095
Windows GPU TensorRT CI Pipeline: onnxruntime/core/mlas/lib/amd64/QgemmU8X8KernelAvx2.asm#L1199
epilog offset from end of function exceeds 4095

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