Matmul nbits to optimize memory layout for avx instructions#22203
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Matmul nbits to optimize memory layout for avx instructions#22203
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Signed-off-by: liqunfu <liqun.fu@microsoft.com>
Signed-off-by: liqunfu <liqun.fu@microsoft.com>
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| TEST(MatMulNBits, LongTestFloat32) { | ||
| // onnxruntime::profiling::Profiler::Profiler::Instance().StartProfiling<char>("profile.json"); |
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Signed-off-by: liqunfu <liqun.fu@microsoft.com>
…hus not to implement avx512 Signed-off-by: liqunfu <liqun.fu@microsoft.com>
… to be in a separate loop. defer this work later Signed-off-by: liqunfu <liqun.fu@microsoft.com>
Signed-off-by: liqunfu <liqun.fu@microsoft.com>
Signed-off-by: liqunfu <liqun.fu@microsoft.com>
Signed-off-by: liqunfu <liqun.fu@microsoft.com>
Signed-off-by: Liqun Fu <liqun.fu@microsoft.com>
Signed-off-by: Liqun Fu <liqun_fu@hotmail.com>
Signed-off-by: Liqun Fu <liqun.fu@microsoft.com>
Signed-off-by: Liqun Fu <liqun.fu@microsoft.com>
Signed-off-by: Liqun Fu <liqun.fu@microsoft.com>
| __m512i sum_16_epi32 = _mm512_madd_epi16(one_32_epi16, sum_32_epi16); | ||
| __m512 sum_16_ps = _mm512_cvtepi32_ps(sum_16_epi32); | ||
| acc = _mm512_fmadd_ps(sum_16_ps, _mm512_set1_ps(combined_scale), acc); | ||
| // acc = _mm512_fmadd_ps(sum_16_ps, load_broadcast_512(combined_scale), acc); |
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| // folowing 2 lines do the same with close perf (more latency count). | ||
| // it requires CPUID Flags: AVX512DQ which is more restricted | ||
| // const __m256 scale_b_ps = _mm256_castpd_ps(_mm256_broadcast_sd(combined_scale)); | ||
| // const __m512 scale_b_16_ps = _mm512_broadcast_f32x8(scale_b_ps); | ||
| // return; |
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Commented-out code
Signed-off-by: Liqun Fu <liqun.fu@microsoft.com>
Signed-off-by: liqunfu <liqun.fu@microsoft.com>
…will not compile on Cuda CI Signed-off-by: liqunfu <liqun.fu@microsoft.com>
Signed-off-by: Liqun Fu <liqun.fu@microsoft.com>
…or>(InputIndex::scales); Signed-off-by: Liqun Fu <liqun.fu@microsoft.com>
Signed-off-by: Liqun Fu <liqun.fu@microsoft.com>
Signed-off-by: Liqun Fu <liqun.fu@microsoft.com>
Signed-off-by: Liqun Fu <liqun.fu@microsoft.com>
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The main purpose of this PR is to remove sqnbit's dependency on sgemm in x86/x64 cases. The benefit is a cleaner memory layout not requiring memory alignment, no need for the Rows by 16-bytes memory layout required by sgemm. It also offers slight performance improvement.
A second improvement in the PR is to reduce memory footprint by fully packing zero point and scales. There is no need for these inputs after they are packed with weights.
The following performance data is to show that new code does not downgrade performance (if not improve):
Avx2 M=1, Asymmetric:
Avx2 M=1, Symmetric:
Avx2 M=128, Asymmetric:
Avx2 M=128, Symmetric:
Avx512vnni M=1, Asymmetric:
Avx512vnni M=1, Symmetric:
Avx512vnni M=128, Asymmetric:
Avx512vnni M=128, Symmetric:
Avx512 M=1, Asymmetric:
Avx512 M=1, Symmetric:
Avx512 M=128, Asymmetric:
Avx512 M=128, Symmetric:
Avx2vnni M=1, Asymmetric:
Avx2vnni M=1, Symmetric:
Avx2vnni M=128, Asymmetric:
Avx2vnni M=128, Symmetric: