8354815: RISC-V: Change type of bitwise rotation shift to iRegIorL2I

Reviewed-by: fyang, fjiang

Author: Anjian-Wen

src/hotspot/cpu/riscv/riscv.ad

@@ -6445,7 +6445,6 @@ instruct addI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAdd src2) %{
   format %{ "addiw  $dst, $src1, $src2\t#@addI_reg_imm" %}
 
   ins_encode %{
-    int32_t con = (int32_t)$src2$$constant;
     __ addiw(as_Register($dst$$reg),
              as_Register($src1$$reg),
              $src2$$constant);
@@ -6507,7 +6506,6 @@ instruct addP_reg_imm(iRegPNoSp dst, iRegP src1, immLAdd src2) %{
   format %{ "addi  $dst, $src1, $src2\t# ptr, #@addP_reg_imm" %}
 
   ins_encode %{
-    // src2 is imm, so actually call the addi
     __ addi(as_Register($dst$$reg),
             as_Register($src1$$reg),
             $src2$$constant);
@@ -6829,7 +6827,7 @@ instruct UmodL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 // Integer Shifts
 
 // Shift Left Register
-// In RV64I, only the low 5 bits of src2 are considered for the shift amount
+// Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
 instruct lShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
   match(Set dst (LShiftI src1 src2));
   ins_cost(ALU_COST);
@@ -6862,7 +6860,7 @@ instruct lShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
 %}
 
 // Shift Right Logical Register
-// In RV64I, only the low 5 bits of src2 are considered for the shift amount
+// Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
 instruct urShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
   match(Set dst (URShiftI src1 src2));
   ins_cost(ALU_COST);
@@ -6895,7 +6893,7 @@ instruct urShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
 %}
 
 // Shift Right Arithmetic Register
-// In RV64I, only the low 5 bits of src2 are considered for the shift amount
+// Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
 instruct rShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
   match(Set dst (RShiftI src1 src2));
   ins_cost(ALU_COST);
@@ -6930,7 +6928,7 @@ instruct rShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
 // Long Shifts
 
 // Shift Left Register
-// In RV64I, only the low 6 bits of src2 are considered for the shift amount
+// Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
 instruct lShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
   match(Set dst (LShiftL src1 src2));
 
@@ -6965,7 +6963,7 @@ instruct lShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
 %}
 
 // Shift Right Logical Register
-// In RV64I, only the low 6 bits of src2 are considered for the shift amount
+// Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
 instruct urShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
   match(Set dst (URShiftL src1 src2));
 
@@ -7018,7 +7016,7 @@ instruct urShiftP_reg_imm(iRegLNoSp dst, iRegP src1, immI src2) %{
 %}
 
 // Shift Right Arithmetic Register
-// In RV64I, only the low 6 bits of src2 are considered for the shift amount
+// Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
 instruct rShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
   match(Set dst (RShiftL src1 src2));
 

src/hotspot/cpu/riscv/riscv_b.ad

@@ -25,7 +25,8 @@
 
 // RISCV Bit-Manipulation Extension Architecture Description File
 
-instruct rorI_imm_b(iRegINoSp dst, iRegI src, immI shift) %{
+// Rotate Right Word Immediate
+instruct rorI_imm_b(iRegINoSp dst, iRegIorL2I src, immI shift) %{
   predicate(UseZbb);
   match(Set dst (RotateRight src shift));
 
@@ -39,6 +40,7 @@ instruct rorI_imm_b(iRegINoSp dst, iRegI src, immI shift) %{
   ins_pipe(ialu_reg_shift);
 %}
 
+// Rotate Right Immediate
 instruct rorL_imm_b(iRegLNoSp dst, iRegL src, immI shift) %{
   predicate(UseZbb);
   match(Set dst (RotateRight src shift));
@@ -53,7 +55,9 @@ instruct rorL_imm_b(iRegLNoSp dst, iRegL src, immI shift) %{
   ins_pipe(ialu_reg_shift);
 %}
 
-instruct rorI_reg_b(iRegINoSp dst, iRegI src, iRegI shift) %{
+// Rotate Right Word Register
+// Only the low 5 bits of shift value are used, all other bits are ignored.
+instruct rorI_reg_b(iRegINoSp dst, iRegIorL2I src, iRegIorL2I shift) %{
   predicate(UseZbb);
   match(Set dst (RotateRight src shift));
 
@@ -65,7 +69,9 @@ instruct rorI_reg_b(iRegINoSp dst, iRegI src, iRegI shift) %{
   ins_pipe(ialu_reg_reg);
 %}
 
-instruct rorL_reg_b(iRegLNoSp dst, iRegL src, iRegI shift) %{
+// Rotate Right Register
+// Only the low 6 bits of shift value are used, all other bits are ignored.
+instruct rorL_reg_b(iRegLNoSp dst, iRegL src, iRegIorL2I shift) %{
   predicate(UseZbb);
   match(Set dst (RotateRight src shift));
 
@@ -77,7 +83,9 @@ instruct rorL_reg_b(iRegLNoSp dst, iRegL src, iRegI shift) %{
   ins_pipe(ialu_reg_reg);
 %}
 
-instruct rolI_reg_b(iRegINoSp dst, iRegI src, iRegI shift) %{
+// Rotate Left Word Register
+// Only the low 5 bits of shift value are used, all other bits are ignored.
+instruct rolI_reg_b(iRegINoSp dst, iRegIorL2I src, iRegIorL2I shift) %{
   predicate(UseZbb);
   match(Set dst (RotateLeft src shift));
 
@@ -89,7 +97,9 @@ instruct rolI_reg_b(iRegINoSp dst, iRegI src, iRegI shift) %{
   ins_pipe(ialu_reg_reg);
 %}
 
-instruct rolL_reg_b(iRegLNoSp dst, iRegL src, iRegI shift) %{
+// Rotate Left Register
+// Only the low 6 bits of shift value are used, all other bits are ignored.
+instruct rolL_reg_b(iRegLNoSp dst, iRegL src, iRegIorL2I shift) %{
   predicate(UseZbb);
   match(Set dst (RotateLeft src shift));
 

src/hotspot/cpu/riscv/riscv_v.ad

@@ -3499,6 +3499,7 @@ instruct vrotate_right(vReg dst, vReg src, vReg shift) %{
   ins_pipe(pipe_slow);
 %}
 
+// Only the low log2(SEW) bits of shift value are used, all other bits are ignored.
 instruct vrotate_right_reg(vReg dst, vReg src, iRegIorL2I shift) %{
   match(Set dst (RotateRightV src (Replicate shift)));
   format %{ "vrotate_right_reg $dst, $src, $shift\t" %}
@@ -3541,6 +3542,7 @@ instruct vrotate_right_masked(vReg dst_src, vReg shift, vRegMask_V0 v0) %{
   ins_pipe(pipe_slow);
 %}
 
+// Only the low log2(SEW) bits of shift value are used, all other bits are ignored.
 instruct vrotate_right_reg_masked(vReg dst_src, iRegIorL2I shift, vRegMask_V0 v0) %{
   match(Set dst_src (RotateRightV (Binary dst_src (Replicate shift)) v0));
   format %{ "vrotate_right_reg_masked $dst_src, $dst_src, $shift, v0.t\t" %}
@@ -3584,6 +3586,7 @@ instruct vrotate_left(vReg dst, vReg src, vReg shift) %{
   ins_pipe(pipe_slow);
 %}
 
+// Only the low log2(SEW) bits of shift value are used, all other bits are ignored.
 instruct vrotate_left_reg(vReg dst, vReg src, iRegIorL2I shift) %{
   match(Set dst (RotateLeftV src (Replicate shift)));
   format %{ "vrotate_left_reg $dst, $src, $shift\t" %}
@@ -3627,6 +3630,7 @@ instruct vrotate_left_masked(vReg dst_src, vReg shift, vRegMask_V0 v0) %{
   ins_pipe(pipe_slow);
 %}
 
+// Only the low log2(SEW) bits of shift value are used, all other bits are ignored.
 instruct vrotate_left_reg_masked(vReg dst_src, iRegIorL2I shift, vRegMask_V0 v0) %{
   match(Set dst_src (RotateLeftV (Binary dst_src (Replicate shift)) v0));
   format %{ "vrotate_left_reg_masked $dst_src, $dst_src, $shift, v0.t\t" %}