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Mohamed IssaSrinivas Vamsi Parasa
Mohamed Issa
authored and
Srinivas Vamsi Parasa
committed
8378295: Update scalar AVX10 floating point min/max definitions
Reviewed-by: sviswanathan, mhaessig, jbhateja, sparasa
1 parent 5164fbc commit 1a99655

11 files changed

Lines changed: 626 additions & 321 deletions

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‎src/hotspot/cpu/x86/assembler_x86.cpp‎

Lines changed: 94 additions & 62 deletions
Original file line numberDiff line numberDiff line change
@@ -3472,22 +3472,52 @@ void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
34723472
emit_int16(0x6F, (0xC0 | encode));
34733473
}
34743474

3475-
void Assembler::vmovw(XMMRegister dst, Register src) {
3475+
void Assembler::evmovw(XMMRegister dst, Register src) {
34763476
assert(VM_Version::supports_avx512_fp16(), "requires AVX512-FP16");
34773477
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
34783478
attributes.set_is_evex_instruction();
34793479
int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_MAP5, &attributes, true);
34803480
emit_int16(0x6E, (0xC0 | encode));
34813481
}
34823482

3483-
void Assembler::vmovw(Register dst, XMMRegister src) {
3483+
void Assembler::evmovw(Register dst, XMMRegister src) {
34843484
assert(VM_Version::supports_avx512_fp16(), "requires AVX512-FP16");
34853485
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
34863486
attributes.set_is_evex_instruction();
34873487
int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_MAP5, &attributes, true);
34883488
emit_int16(0x7E, (0xC0 | encode));
34893489
}
34903490

3491+
void Assembler::evmovw(XMMRegister dst, Address src) {
3492+
assert(VM_Version::supports_avx10_2(), "");
3493+
InstructionMark im(this);
3494+
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3495+
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3496+
attributes.set_is_evex_instruction();
3497+
vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_MAP5, &attributes);
3498+
emit_int8(0x6E);
3499+
emit_operand(dst, src, 0);
3500+
}
3501+
3502+
void Assembler::evmovw(Address dst, XMMRegister src) {
3503+
assert(VM_Version::supports_avx10_2(), "");
3504+
InstructionMark im(this);
3505+
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3506+
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3507+
attributes.set_is_evex_instruction();
3508+
vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_MAP5, &attributes);
3509+
emit_int8(0x7E);
3510+
emit_operand(src, dst, 0);
3511+
}
3512+
3513+
void Assembler::evmovw(XMMRegister dst, XMMRegister src) {
3514+
assert(VM_Version::supports_avx10_2(), "");
3515+
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3516+
attributes.set_is_evex_instruction();
3517+
int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_MAP5, &attributes);
3518+
emit_int16(0x6E, (0xC0 | encode));
3519+
}
3520+
34913521
void Assembler::vmovdqu(XMMRegister dst, Address src) {
34923522
assert(UseAVX > 0, "");
34933523
InstructionMark im(this);
@@ -7310,6 +7340,42 @@ void Assembler::etzcntq(Register dst, Address src, bool no_flags) {
73107340
emit_operand(dst, src, 0);
73117341
}
73127342

7343+
void Assembler::evucomish(XMMRegister dst, Address src) {
7344+
InstructionMark im(this);
7345+
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7346+
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
7347+
attributes.set_is_evex_instruction();
7348+
vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_MAP5, &attributes);
7349+
emit_int8(0x2E);
7350+
emit_operand(dst, src, 0);
7351+
}
7352+
7353+
void Assembler::evucomish(XMMRegister dst, XMMRegister src) {
7354+
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7355+
attributes.set_is_evex_instruction();
7356+
int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_MAP5, &attributes);
7357+
emit_int16(0x2E, (0xC0 | encode));
7358+
}
7359+
7360+
void Assembler::evucomxsh(XMMRegister dst, Address src) {
7361+
assert(VM_Version::supports_avx10_2(), "");
7362+
InstructionMark im(this);
7363+
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7364+
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
7365+
attributes.set_is_evex_instruction();
7366+
vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_MAP5, &attributes);
7367+
emit_int8(0x2E);
7368+
emit_operand(dst, src, 0);
7369+
}
7370+
7371+
void Assembler::evucomxsh(XMMRegister dst, XMMRegister src) {
7372+
assert(VM_Version::supports_avx10_2(), "");
7373+
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7374+
attributes.set_is_evex_instruction();
7375+
int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_MAP5, &attributes);
7376+
emit_int16(0x2E, (0xC0 | encode));
7377+
}
7378+
73137379
void Assembler::ucomisd(XMMRegister dst, Address src) {
73147380
InstructionMark im(this);
73157381
InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
@@ -7327,7 +7393,7 @@ void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
73277393
emit_int16(0x2E, (0xC0 | encode));
73287394
}
73297395

7330-
void Assembler::vucomxsd(XMMRegister dst, Address src) {
7396+
void Assembler::evucomxsd(XMMRegister dst, Address src) {
73317397
assert(VM_Version::supports_avx10_2(), "");
73327398
InstructionMark im(this);
73337399
InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
@@ -7338,7 +7404,7 @@ void Assembler::vucomxsd(XMMRegister dst, Address src) {
73387404
emit_operand(dst, src, 0);
73397405
}
73407406

7341-
void Assembler::vucomxsd(XMMRegister dst, XMMRegister src) {
7407+
void Assembler::evucomxsd(XMMRegister dst, XMMRegister src) {
73427408
assert(VM_Version::supports_avx10_2(), "");
73437409
InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
73447410
attributes.set_is_evex_instruction();
@@ -7361,7 +7427,7 @@ void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
73617427
emit_int16(0x2E, (0xC0 | encode));
73627428
}
73637429

7364-
void Assembler::vucomxss(XMMRegister dst, Address src) {
7430+
void Assembler::evucomxss(XMMRegister dst, Address src) {
73657431
assert(VM_Version::supports_avx10_2(), "");
73667432
InstructionMark im(this);
73677433
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
@@ -7372,7 +7438,7 @@ void Assembler::vucomxss(XMMRegister dst, Address src) {
73727438
emit_operand(dst, src, 0);
73737439
}
73747440

7375-
void Assembler::vucomxss(XMMRegister dst, XMMRegister src) {
7441+
void Assembler::evucomxss(XMMRegister dst, XMMRegister src) {
73767442
assert(VM_Version::supports_avx10_2(), "");
73777443
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
73787444
attributes.set_is_evex_instruction();
@@ -8411,30 +8477,6 @@ void Assembler::vmulsh(XMMRegister dst, XMMRegister nds, XMMRegister src) {
84118477
emit_int16(0x59, (0xC0 | encode));
84128478
}
84138479

8414-
void Assembler::vmaxsh(XMMRegister dst, XMMRegister nds, XMMRegister src) {
8415-
assert(VM_Version::supports_avx512_fp16(), "requires AVX512-FP16");
8416-
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8417-
attributes.set_is_evex_instruction();
8418-
int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_MAP5, &attributes);
8419-
emit_int16(0x5F, (0xC0 | encode));
8420-
}
8421-
8422-
void Assembler::eminmaxsh(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
8423-
assert(VM_Version::supports_avx10_2(), "");
8424-
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8425-
attributes.set_is_evex_instruction();
8426-
int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3A, &attributes);
8427-
emit_int24(0x53, (0xC0 | encode), imm8);
8428-
}
8429-
8430-
void Assembler::vminsh(XMMRegister dst, XMMRegister nds, XMMRegister src) {
8431-
assert(VM_Version::supports_avx512_fp16(), "requires AVX512-FP16");
8432-
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8433-
attributes.set_is_evex_instruction();
8434-
int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_MAP5, &attributes);
8435-
emit_int16(0x5D, (0xC0 | encode));
8436-
}
8437-
84388480
void Assembler::vsqrtsh(XMMRegister dst, XMMRegister src) {
84398481
assert(VM_Version::supports_avx512_fp16(), "requires AVX512-FP16");
84408482
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
@@ -13369,48 +13411,38 @@ bool Assembler::is_demotable(bool no_flags, int dst_enc, int nds_enc) {
1336913411
return (!no_flags && dst_enc == nds_enc);
1337013412
}
1337113413

13372-
void Assembler::vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
13373-
assert(VM_Version::supports_avx(), "");
13374-
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13375-
int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
13376-
emit_int16(0x5F, (0xC0 | encode));
13377-
}
13378-
13379-
void Assembler::vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
13380-
assert(VM_Version::supports_avx(), "");
13381-
InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13382-
attributes.set_rex_vex_w_reverted();
13383-
int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
13384-
emit_int16(0x5F, (0xC0 | encode));
13385-
}
13386-
13387-
void Assembler::vminss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
13388-
assert(VM_Version::supports_avx(), "");
13389-
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13390-
int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
13391-
emit_int16(0x5D, (0xC0 | encode));
13414+
void Assembler::evminmaxsh(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int imm8) {
13415+
assert(VM_Version::supports_avx10_2(), "");
13416+
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
13417+
attributes.set_is_evex_instruction();
13418+
attributes.set_embedded_opmask_register_specifier(mask);
13419+
if (merge) {
13420+
attributes.reset_is_clear_context();
13421+
}
13422+
int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3A, &attributes);
13423+
emit_int24(0x53, (0xC0 | encode), imm8);
1339213424
}
1339313425

13394-
void Assembler::eminmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
13426+
void Assembler::evminmaxss(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int imm8) {
1339513427
assert(VM_Version::supports_avx10_2(), "");
13396-
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13428+
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1339713429
attributes.set_is_evex_instruction();
13430+
attributes.set_embedded_opmask_register_specifier(mask);
13431+
if (merge) {
13432+
attributes.reset_is_clear_context();
13433+
}
1339813434
int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
1339913435
emit_int24(0x53, (0xC0 | encode), imm8);
1340013436
}
1340113437

13402-
void Assembler::vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
13403-
assert(VM_Version::supports_avx(), "");
13404-
InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13405-
attributes.set_rex_vex_w_reverted();
13406-
int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
13407-
emit_int16(0x5D, (0xC0 | encode));
13408-
}
13409-
13410-
void Assembler::eminmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
13438+
void Assembler::evminmaxsd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int imm8) {
1341113439
assert(VM_Version::supports_avx10_2(), "");
13412-
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13440+
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1341313441
attributes.set_is_evex_instruction();
13442+
attributes.set_embedded_opmask_register_specifier(mask);
13443+
if (merge) {
13444+
attributes.reset_is_clear_context();
13445+
}
1341413446
int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
1341513447
emit_int24(0x53, (0xC0 | encode), imm8);
1341613448
}

‎src/hotspot/cpu/x86/assembler_x86.hpp‎

Lines changed: 18 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1694,8 +1694,11 @@ class Assembler : public AbstractAssembler {
16941694
void movsbl(Register dst, Address src);
16951695
void movsbl(Register dst, Register src);
16961696

1697-
void vmovw(XMMRegister dst, Register src);
1698-
void vmovw(Register dst, XMMRegister src);
1697+
void evmovw(XMMRegister dst, Register src);
1698+
void evmovw(Register dst, XMMRegister src);
1699+
void evmovw(XMMRegister dst, Address src);
1700+
void evmovw(Address dst, XMMRegister src);
1701+
void evmovw(XMMRegister dst, XMMRegister src);
16991702

17001703
void movsbq(Register dst, Address src);
17011704
void movsbq(Register dst, Register src);
@@ -2329,17 +2332,23 @@ class Assembler : public AbstractAssembler {
23292332
void tzcntq(Register dst, Address src);
23302333
void etzcntq(Register dst, Address src, bool no_flags);
23312334

2335+
// Unordered Compare Scalar Half-Precision Floating-Point Values and set EFLAGS
2336+
void evucomish(XMMRegister dst, Address src);
2337+
void evucomish(XMMRegister dst, XMMRegister src);
2338+
void evucomxsh(XMMRegister dst, Address src);
2339+
void evucomxsh(XMMRegister dst, XMMRegister src);
2340+
23322341
// Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
23332342
void ucomisd(XMMRegister dst, Address src);
23342343
void ucomisd(XMMRegister dst, XMMRegister src);
2335-
void vucomxsd(XMMRegister dst, Address src);
2336-
void vucomxsd(XMMRegister dst, XMMRegister src);
2344+
void evucomxsd(XMMRegister dst, Address src);
2345+
void evucomxsd(XMMRegister dst, XMMRegister src);
23372346

23382347
// Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
23392348
void ucomiss(XMMRegister dst, Address src);
23402349
void ucomiss(XMMRegister dst, XMMRegister src);
2341-
void vucomxss(XMMRegister dst, Address src);
2342-
void vucomxss(XMMRegister dst, XMMRegister src);
2350+
void evucomxss(XMMRegister dst, Address src);
2351+
void evucomxss(XMMRegister dst, XMMRegister src);
23432352

23442353
void xabort(int8_t imm8);
23452354

@@ -2417,11 +2426,6 @@ class Assembler : public AbstractAssembler {
24172426
void vsubss(XMMRegister dst, XMMRegister nds, Address src);
24182427
void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
24192428

2420-
void vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2421-
void vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2422-
void vminss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2423-
void vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2424-
24252429
void sarxl(Register dst, Register src1, Register src2);
24262430
void sarxl(Register dst, Address src1, Register src2);
24272431
void sarxq(Register dst, Register src1, Register src2);
@@ -2552,8 +2556,6 @@ class Assembler : public AbstractAssembler {
25522556
void vsubsh(XMMRegister dst, XMMRegister nds, XMMRegister src);
25532557
void vmulsh(XMMRegister dst, XMMRegister nds, XMMRegister src);
25542558
void vdivsh(XMMRegister dst, XMMRegister nds, XMMRegister src);
2555-
void vmaxsh(XMMRegister dst, XMMRegister nds, XMMRegister src);
2556-
void vminsh(XMMRegister dst, XMMRegister nds, XMMRegister src);
25572559
void vsqrtsh(XMMRegister dst, XMMRegister src);
25582560
void vfmadd132sh(XMMRegister dst, XMMRegister src1, XMMRegister src2);
25592561

@@ -2790,9 +2792,9 @@ class Assembler : public AbstractAssembler {
27902792
void vminpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
27912793

27922794
// AVX10.2 floating point minmax instructions
2793-
void eminmaxsh(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);
2794-
void eminmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);
2795-
void eminmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);
2795+
void evminmaxsh(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int imm8);
2796+
void evminmaxss(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int imm8);
2797+
void evminmaxsd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int imm8);
27962798
void evminmaxph(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int imm8, int vector_len);
27972799
void evminmaxph(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int imm8, int vector_len);
27982800
void evminmaxps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int imm8, int vector_len);

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