8381617: vm_version_windows_aarch64.cpp: PF_ARM_SVE_INSTRUCTIONS_AVAILABLE undeclared identifier

Reviewed-by: kvn, macarte

Author: raneashay

src/hotspot/os_cpu/windows_aarch64/sve_windows_aarch64.S

@@ -24,19 +24,26 @@
     ; Support for int get_sve_vector_length();
     ;
     ; Returns the current SVE vector length in bytes.
-    ; This function uses the INCB instruction which increments a register
-    ; by the number of bytes in an SVE vector register.
+    ; This function uses the RDVL instruction which reads a multiple of the
+    ; vector register size into a scalar register.
     ;
-    ; Note: This function will fault if SVE is not available or enabled.
-    ; The caller must ensure SVE support is detected before calling.
+    ; Note: This function will fault if SVE is not available or enabled.  The
+    ; caller must ensure SVE support is detected before calling.
 
     ALIGN  4
     EXPORT get_sve_vector_length
     AREA sve_text, CODE
 
 get_sve_vector_length
-    mov      x0, #0
-    incb     x0
+    ; Older versions of Visual Studio aren't aware of SVE mnemonics, so we use
+    ; the raw instruction encoding to satisfy the compiler.  This function call
+    ; is gated by `VM_Version::supports_sve()`, so this instruction will never
+    ; run on non-SVE hardware.
+    ;
+    ; See https://www.scs.stanford.edu/~zyedidia/arm64/rdvl_r_i.html for a quick
+    ; reference to the instruction encoding.
+
+    DCD      0x04BF5020   ; rdvl x0, #1 (i.e. x0 = 1 * vector_length_in_bytes)
     ret
 
     END

src/hotspot/os_cpu/windows_aarch64/vm_version_windows_aarch64.cpp

@@ -26,19 +26,52 @@
 #include "runtime/os.hpp"
 #include "runtime/vm_version.hpp"
 
-// Assembly function to get SVE vector length using INCB instruction
+// Since PF_ARM_SVE_INSTRUCTIONS_AVAILABLE and related constants were added in
+// Windows 11 (version 24H2) and in Windows Server 2025, we define them here for
+// compatibility with older SDK versions.
+#ifndef PF_ARM_SVE_INSTRUCTIONS_AVAILABLE
+#define PF_ARM_SVE_INSTRUCTIONS_AVAILABLE 46
+#endif
+
+#ifndef PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE
+#define PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE 47
+#endif
+
+#ifndef PF_ARM_SVE_BITPERM_INSTRUCTIONS_AVAILABLE
+#define PF_ARM_SVE_BITPERM_INSTRUCTIONS_AVAILABLE 51
+#endif
+
+#ifndef PF_ARM_SHA3_INSTRUCTIONS_AVAILABLE
+#define PF_ARM_SHA3_INSTRUCTIONS_AVAILABLE 64
+#endif
+
+#ifndef PF_ARM_SHA512_INSTRUCTIONS_AVAILABLE
+#define PF_ARM_SHA512_INSTRUCTIONS_AVAILABLE 65
+#endif
+
+#ifndef PF_ARM_V82_FP16_INSTRUCTIONS_AVAILABLE
+#define PF_ARM_V82_FP16_INSTRUCTIONS_AVAILABLE 67
+#endif
+
+// Assembly function to get SVE vector length using RDVL instruction
 extern "C" int get_sve_vector_length();
 
 int VM_Version::get_current_sve_vector_length() {
   assert(VM_Version::supports_sve(), "should not call this");
-  // Use assembly instruction to get the actual SVE vector length
-  return  VM_Version::supports_sve() ? get_sve_vector_length() : 0; // This value is in bytes
+  return VM_Version::supports_sve() ? get_sve_vector_length() : 0;
 }
 
 int VM_Version::set_and_get_current_sve_vector_length(int length) {
   assert(VM_Version::supports_sve(), "should not call this");
-  // Use assembly instruction to get the SVE vector length
-  return VM_Version::supports_sve() ? get_sve_vector_length() : 0; // This value is in bytes
+
+  // Unlike Linux, Windows does not present a way to modify the VL (the
+  // rationale is that the OS expects the application to use the maximum vector
+  // length supported by the hardware), so we simply return the current VL.  If
+  // the user sets `MaxVectorSize` that is not the same as the maximum possible
+  // vector length, then the caller (`VM_Version::initialize()`) will print a
+  // warning, set `MaxVectorSize` to the value returned by this function, and
+  // move on.
+  return VM_Version::supports_sve() ? get_sve_vector_length() : 0;
 }
 
 void VM_Version::get_os_cpu_info() {
@@ -67,6 +100,10 @@ void VM_Version::get_os_cpu_info() {
   if (IsProcessorFeaturePresent(PF_ARM_SVE_BITPERM_INSTRUCTIONS_AVAILABLE)) {
     set_feature(CPU_SVEBITPERM);
   }
+  if (IsProcessorFeaturePresent(PF_ARM_V82_FP16_INSTRUCTIONS_AVAILABLE)) {
+    set_feature(CPU_FPHP);
+    set_feature(CPU_ASIMDHP);
+  }
   if (IsProcessorFeaturePresent(PF_ARM_SHA3_INSTRUCTIONS_AVAILABLE)) {
     set_feature(CPU_SHA3);
   }

test/hotspot/jtreg/compiler/c2/irTests/TestFloat16ScalarOperations.java

@@ -24,7 +24,7 @@
 
 /**
 * @test
-* @bug 8308363 8336406
+* @bug 8308363 8336406 8381617
 * @summary Validate compiler IR for various Float16 scalar operations.
 * @modules jdk.incubator.vector
 * @requires vm.compiler2.enabled
@@ -714,9 +714,13 @@ public void testSqrtConstantFolding() {
 
     @Test
     @IR(counts = {IRNode.FMA_HF, " 0 ", IRNode.REINTERPRET_S2HF, " 0 ", IRNode.REINTERPRET_HF2S, " 0 "},
-        applyIfCPUFeatureOr = {"avx512_fp16", "true", "zfh", "true"})
+        applyIfCPUFeatureOr = {"avx512_fp16", "true", "zfh", "true"},
+        // On Windows, both GCC and MSVC don't set __STDC_IEC_559__, so FMAs on constants are not folded.
+        applyIfPlatform = {"windows", "false"})
     @IR(counts = {IRNode.FMA_HF, " 0 ", IRNode.REINTERPRET_S2HF, " 0 ", IRNode.REINTERPRET_HF2S, " 0 "},
-        applyIfCPUFeatureAnd = {"fphp", "true", "asimdhp", "true"})
+        applyIfCPUFeatureAnd = {"fphp", "true", "asimdhp", "true"},
+        // On Windows, both GCC and MSVC don't set __STDC_IEC_559__, so FMAs on constants are not folded.
+        applyIfPlatform = {"windows", "false"})
     @Warmup(10000)
     public void testFMAConstantFolding() {
         // If any argument is NaN, the result is NaN.
@@ -752,9 +756,13 @@ public void testFMAConstantFolding() {
 
     @Test
     @IR(failOn = {IRNode.ADD_HF, IRNode.SUB_HF, IRNode.MUL_HF, IRNode.DIV_HF, IRNode.SQRT_HF, IRNode.FMA_HF},
-        applyIfCPUFeatureOr = {"avx512_fp16", "true", "zfh", "true"})
+        applyIfCPUFeatureOr = {"avx512_fp16", "true", "zfh", "true"},
+        // On Windows, both GCC and MSVC don't set __STDC_IEC_559__, so FMAs on constants are not folded.
+        applyIfPlatform = {"windows", "false"})
     @IR(failOn = {IRNode.ADD_HF, IRNode.SUB_HF, IRNode.MUL_HF, IRNode.DIV_HF, IRNode.SQRT_HF, IRNode.FMA_HF},
-        applyIfCPUFeatureAnd = {"fphp", "true", "asimdhp", "true"})
+        applyIfCPUFeatureAnd = {"fphp", "true", "asimdhp", "true"},
+        // On Windows, both GCC and MSVC don't set __STDC_IEC_559__, so FMAs on constants are not folded.
+        applyIfPlatform = {"windows", "false"})
     @Warmup(10000)
     public void testRounding1() {
         dst[0] = float16ToRawShortBits(add(RANDOM1, RANDOM2));