Incorrect voter wiring and rip-up in `cones_min.ys`

[mlyoung101]

This is the important part of the diagram:

Basically the problems are:

1. Incorrect error signal writing by voter_builder, why are we connecting ERR_INTER_OUT to ERR_INTERMEDIATE, and why is it not being connected to the global ERR signal and or'd then reduced together?
2. We are disconnecting the 0\stage1 wire, which is OK, but we're not re-attaching it for some reason
3. On the above, voter output is incorrect, it should be going to stage1, not the ERR_INTER_OUT

[mlyoung101]

Noting that it seems fine when we rip up two of the inputs to the DFF:

But when we rip up the third, everything goes to shite:

Now this could still be OK, it's just a weird layout problem. The issue is, however, that we're forgetting about $0\stage1[0:0] at some point.

How do we tackle this? Maybe extractReplicaWires needs to remember what it rips up? Why does this work for other cases, but not for this specific case?

I also tried getting rid of extractReplicaWire on the branch sigspec-replicawires-rewrite to use RTLIL::SigSpec directly, but there are a lot of problems dealing with chunks, and we still have to abuse sigSpecToWire a lot. I think the general idea of ripping up ports and putting in our own logic is acceptable, we just have to do it correctly.