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Merge pull request #279 from modelica/pu/klausschuch/clock_variables
Call clocks clocks instead of clock variables
2 parents bcb851c + 4f217a0 commit af58d22

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docs/1____introduction.adoc

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@@ -23,6 +23,8 @@ So that this layered standard can be supported in a variety of FMU importers and
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* Direct Communication: Limited to exactly two FMUs and uses a common FMU importer that does not require any special features for simulating buses.
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The importer only needs to support FMI variables, Clocks, and terminals, which are sufficient to emulate bus communication between the FMUs.
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Note, even though Clocks are listed in the `ModelVariables` element in the `modelDescription.xml` of the FMU, Clocks will be treated differently than all other variables.
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In this document we will call variables of type Clock 'Clocks', and all variables that are not Clocks 'variables'.
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* Composition with dedicated Bus Simulation FMU: A separate Bus Simulation FMU is used to simulate the specific bus behavior.
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Other FMUs that want to emulate bus communication provide and relate network information via this Bus Simulation FMU.
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This communication architecture can be operated by a common FMU importer and allows complex and detailed bus simulations.

docs/2____common_concepts.adoc

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docs/3____physical_signal_abstraction.adoc

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To allow importers an easy distinction between these FMU roles, for Bus Simulation FMUs the attribute `isBusSimulationFMU` shall be set to `true` in the Manifest file.
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The figure below shows an example architecture of a Physical Signal Abstraction.
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The signals (_Signal 1...8_) are modeled as clocked FMU variables of a specific type.
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The signals (_Signal 1...8_) are modeled as clocked variables of a specific type.
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The corresponding signals are structurally combined using Protocol Data Units (PDUs), which in turn are assigned to frames.
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The PDU and frame structuring is done via terminals (_PDU A, B, C_ and _Frame X, Y_).
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The respective FMU variables are connected to a Bus Simulation, which emulates them according to their own needs for e.g. according to accuracy.
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The respective variables are connected to a Bus Simulation, which emulates them according to their own needs for e.g. according to accuracy.
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.Physical Signal Abstraction example architecture.
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[#figure-transmission-high-cut-overview]
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image::high_cut_network_fmu.svg[width=80%, align="center"]
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=== Variables [[high-cut-variables]]
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This section explains the variable types used to carry network traffic through FMI variables.
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==== Signal Variables [[high-cut-signal-variables]]
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=== Signal Variables [[high-cut-signal-variables]]
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To define the Physical Signal Abstraction layer, signal variables are used.
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A signal variable carries the physical value of a network signal normally packaged inside a PDU or frame.
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All signal variables are clocked to indicate when they have been sent/received, see <<high-cut-clock-variables>>.
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==== Clock Variables [[high-cut-clock-variables]]
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=== Clocks [[high-cut-clock-variables]]
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In order to use FMU input and output variables as transport layer for networks, Clocks are used to indicate the timing.
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Such a Clock is scheduled by the sending FMU to indicate the transmission of the corresponding frame or frames.
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The sending FMU uses a Clock to indicate the transmission of the corresponding frame or frames.
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The Clock type (`periodic` or `aperiodic`) is defined by the sending FMU.
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_[This allows the FMU (or better the exporting tool) to balance the accuracy and performance of its network communication:_
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_- While `aperiodic` Clocks allow very accurate network simulations, frequently entering `Event Mode` might reduce the network simulation speed._
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_- Using `periodic` Clocks might reduces the number of `Event Modes` required and might speeds up the simulation at the cost of simulation accuracy, because timing must be forced into a fixed grid and some intermediate values might not be transmitted._
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_- One could use (structural) parameters to define the accuracy of `aperiodic` Clocks, allowing control of the simulation accuracy and performance with the same FMU._
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_Note: The statements regarding `aperiodic` and `periodic` Clocks and their impact on performance should be understood as general tendencies rather than universally valid truths, as other aspects such as baud rates and expected bus loads must be taken into account for a more precise estimate.]_
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The Clocks of a receiving frame shall be `triggered` Clocks if they are to be driven by the respective Clock of the sending frame.
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Alternatively, Clocks of a receiving frame can be `periodic` Clocks matching the relevant Clock of the sending frame, which causes them to be scheduled for the same time instances
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The Clocks of a receiving frame shall be `triggered` Clocks if they are to be driven by the respective Clock of the sending frame. +
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Alternatively, Clocks of a receiving frame can be `periodic` Clocks matching the relevant Clock of the sending frame, which causes them to be scheduled for the same time instances.
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_[This may allow for more efficient simulation in the case that there exists a more or less static communications schedule, and more detailed simulation of timing variation is not needed.]_
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Signal variables belonging to frame `BusName.FrameName` and all its variables must share the same `causality` (`input` or `output`).
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Signal variables belonging to frame `BusName.FrameName` must share the same `causality` (`input` or `output`).
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=== Network Description Files [[high-cut-network-description-files,network description file]]
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Standardized <<high-cut-network-description-files,network description files>> may optionally be shipped with each FMU to describe properties of signals and frames, such as signal units, frame composition and trigger conditions.
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* `name` is the network name, e.g., `Powertrain`, see <<high-cut-examples, examples>> and constraints above.
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Element definitions::
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* All signal and Clock variables related to the Physical Signal Abstraction in the `modelDescription.xml` must be covered by a `<Terminal>` element representing the network frame the signals belong to.
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* All signal variables and Clocks related to the Physical Signal Abstraction in the `modelDescription.xml` must be covered by a `<Terminal>` element representing the network frame the signals belong to.
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Annotation element::
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* If a <<high-cut-network-description-files,network description file>> is shipped with the specified FMU, there must be an `<Annotation>` element defining which node or nodes (as comma-separated list without spaces) of the <<high-cut-network-description-files>> are wrapped inside the FMU.
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* `variableName` refers to the input or output variable name of the FMU.
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These variables represent the Physical Signal Abstraction layer.
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Unless there are other requirements, it is recommended to build the variable names as follows: `BusName.FrameName.PDUName.SignalName`, e.g., `Powertrain.tcuSensors.tcuSensors.vCar`.
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This approach automatically provides unique names for all bus-related variables, and can also be used for the Clock variables, to allow automatic grouping by non-terminal-aware tools.
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This approach automatically provides unique names for all bus-related variables, and can also be used for Clocks, to allow automatic grouping by non-terminal-aware tools.
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* `memberName` is the `SignalName` as given in the <<high-cut-network-description-files>>, e.g., `vCar`, if given.
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This is redundant information but simplifies signal name extraction.
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* `variableKind` is `signal`.

docs/4_4_1_can.adoc

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====== Format Error [[low-cut-can-format-error-operation]]
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Represents a format error that indicates a syntax or content error of receiving operations.
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See <<low-cut-format-error-operation, `Format Error`>> for definition.
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====== Arbitration Lost [[low-cut-can-arbitration-lost-operation]]

docs/4_4_2_lin.adoc

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|====
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====== Format Error [[low-cut-lin-format-error-operation]]
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Represents a format error that indicates a syntax or content error of receiving operations.
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See <<low-cut-format-error-operation, `Format Error`>> for definition.
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====== Bus Error [[low-cut-lin-bus-error-operation]]

docs/4_4_3_flexray.adoc

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|====
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====== Format Error [[low-cut-flexray-format-error-operation]]
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A format error indicates a syntax or content error in response to a received operation.
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See <<low-cut-format-error-operation, `Format Error`>> for definition.
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====== Bus Error [[low-cut-flexray-bus-error-operation]]
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This behavior is defined more specifically and slightly differently depending on whether it is a static or dynamic segment.
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What both segments have in common is that the Network FMU itself must know the appropriate time of a <<low-cut-flexray-transmit-operation, `Transmit`>> operation basing on the FlexRay cycle and slot principle.
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In concrete terms, this means that a Network FMU itself must provide the expected <<low-cut-flexray-transmit-operation, `Transmit`>> operation at the appropriate time via <<low-cut-tx-clock-variables, Tx Clock Variables>>.
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In concrete terms, this means that a Network FMU itself must provide the expected <<low-cut-flexray-transmit-operation, `Transmit`>> operation at the appropriate time via <<low-cut-tx-clock, Tx Clocks>>.
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The start time of the first FlexRay cycle is defined by the `Start Time` argument value of the <<low-cut-flexray-start-communication-operation, `Start Communication`>> operation.
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That concrete means that the point in time for the start of FlexRay cycle in nanoseconds can be computed within a Network FMU as

docs/4_4_4_ethernet_operations.adoc

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====== Format Error [[low-cut-ethernet-format-error-operation]]
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Represents a format error that indicates a syntax or content error of receiving operations.
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See <<low-cut-format-error-operation, `Format Error`>> for definition.
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====== Bus Error [[low-cut-ethernet-bus-error-operation]]

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