config.yaml

meta:
  version: 2
  flow: Classic
  substituting_steps:
    # Greyhound uses a padring instead of pins
    OpenROAD.GlobalPlacementSkipIO: null
    OpenROAD.IOPlacement: null
    +Odb.SetPowerConnections: OpenROAD.Padring

    # ECO diodes
    #+OpenROAD.DetailedRouting: Odb.InsertECODiodes
    +OpenROAD.GlobalRouting: Odb.InsertECODiodes
    
    # ECO buffers
    # TODO OpenROAD.ResizerTimingPostGRT
    +OpenROAD.CTS: Odb.InsertECOBuffers
    
    # Add Seal Ring
    +Checker.XOR: KLayout.SealRing
    
    # Save time
    OpenROAD.STAPrePNR: null
    OpenROAD.STAMidPNR*: null
    
    # Run Filler insertion
    # This is done manually for now
    #+KLayout.SealRing: KLayout.FillerGeneration
        
    # Magic reports some overlaps which can be ignored
    Checker.IllegalOverlap: null
    
    # Some warnings in the SoC
    # GL simulation is fine
    Checker.YosysSynthChecks: null
    
    # Setup violations don't matter (for now)
    Checker.SetupViolations: null
    
    # Save time
    
    #Magic.SpiceExtraction: null
    #Netgen.LVS: null
    
    Magic.WriteLEF: null
    Odb.CheckDesignAntennaProperties: null # requires LEF
    
    KLayout.DRC: null
    Magic.DRC: null

DESIGN_NAME: FMD_QNC_greyhound_ihp
VERILOG_FILES:
# PACKAGES
- dir::src/soc/soc_pkg.sv
- dir::src/soc/cf_math_pkg.sv
- dir::ip/cv32e40x/rtl/include/cv32e40x_pkg.sv
- dir::ip/obi/src/obi_pkg.sv
# RTL_OBI
- dir::ip/obi/src/obi_intf.sv
- dir::ip/obi/src/obi_mux.sv
- dir::ip/obi/src/obi_demux.sv
- dir::ip/obi/src/obi_err_sbr.sv
- dir::ip/obi/src/obi_sram_shim.sv
# RTL_COMMON
- dir::ip/common_cells/src/fifo_v3.sv
- dir::ip/common_cells/src/rr_arb_tree.sv
- dir::ip/common_cells/src/delta_counter.sv
- dir::ip/common_cells/src/lzc.sv
# Core and SoC
- dir::ip/cv32e40x/rtl/*.sv
- dir::src/soc/greyhound_soc.sv
- dir::src/soc/dummy_extension.sv
- dir::src/soc/fabric_extension.sv
- dir::src/soc/obi2ahbm_adapter.sv
- dir::src/soc/cv32e40x_clock_gate.sv
# Chip
- dir::src/FMD_QNC_greyhound_ihp.v
- dir::src/greyhound_ihp.sv
# Fabric Wrapper
- dir::ip/fabric/rtl/fabric_wrapper.sv
# Fabric Config
- dir::ip/fabric_config/fabric_config.sv
- dir::ip/fabric_config/fabric_spi_controller.sv
- dir::ip/fabric_config/fabric_spi_receiver.sv
# SQPI XiP
- dir::ip/EF_QSPI_XIP_CTRL/hdl/rtl/EF_QSPI_XIP_CTRL.v
- dir::ip/EF_QSPI_XIP_CTRL/hdl/rtl/DMC.v
- dir::ip/EF_QSPI_XIP_CTRL/hdl/rtl/bus_wrappers/EF_QSPI_XIP_CTRL_AHBL.v
# QSPI PSRAM
- dir::ip/EF_PSRAM_CTRL/hdl/rtl/EF_PSRAM_CTRL.v
- dir::ip/EF_PSRAM_CTRL/hdl/rtl/bus_wrapper/EF_PSRAM_CTRL_AHBL.v
# UART
- dir::ip/EF_UART/hdl/rtl/EF_UART.v
- dir::ip/EF_UART/hdl/rtl/bus_wrappers/EF_UART_AHBL.v
# Util
- dir::ip/EF_IP_UTIL/hdl/ef_util_lib.v

# INCLUDES
VERILOG_INCLUDE_DIRS:
- dir::ip/obi/include/
- dir::ip/common_cells/include/

USE_SLANG: True
SLANG_ARGUMENTS: ['--ignore-assertions', '--keep-hierarchy']

SYNTH_HIERARCHY_MODE: flatten

SYNTH_KEEP_HIERARCHY_MIN_COST: 3000
#SYNTH_KEEP_HIERARCHY_INSTANCES:
SYNTH_KEEP_HIERARCHY_MODULES:
- "\\fabric_config$FMD_QNC_greyhound_ihp.i_greyhound_ihp.fabric_config"

VERILOG_DEFINES:
- FUNCTIONAL
- PnR

LINTER_DISABLE_WARNINGS:
- DECLFILENAME
- EOFNEWLINE
- PINCONNECTEMPTY
- TIMESCALEMOD
- GENUNNAMED

#LINTER_VLT: dir::_deps.vlt

# Debugging
SET_RC_VERBOSE: True

# Select the minimal runset
KLAYOUT_DRC_RUNSET: pdk_dir::/libs.tech/klayout/tech/drc/sg13g2_minimal.lydrc

# Magic has an offset on the SRAMs
PRIMARY_GDSII_STREAMOUT_TOOL: klayout
# Save on file space by sharing same cells
KLAYOUT_CONFLICT_RESOLUTION: SkipNewCell

# Bondpad is not yet included in the PDK
EXTRA_GDS:
- dir::ip/bondpad_70x70/bondpad_70x70.gds

EXTRA_LEFS:
- dir::ip/bondpad_70x70/bondpad_70x70.lef

# SDC
PNR_SDC_FILE: dir::constraint.sdc
SIGNOFF_SDC_FILE: dir::constraint.sdc
FALLBACK_SDC: dir::constraint.sdc

# Power nets
VDD_NETS:
- VDD
GND_NETS:
- VSS

# Perform extraction using the LEF/DEF
MAGIC_EXT_USE_GDS: false

IGNORE_DISCONNECTED_MODULES:
# Ignore missing power pins
- bondpad_70x70

# The IO cells do not extract properly yet
MAGIC_EXT_ABSTRACT_CELLS:
- bondpad_70x70
- sg13g2_IOPadInOut30mA
- sg13g2_IOPadIn
- sg13g2_IOPadOut30mA
- sg13g2_IOPadIOVdd
- sg13g2_IOPadIOVss
- sg13g2_IOPadVss
- sg13g2_IOPadVdd

# Due to thin core area ring
GRT_ALLOW_CONGESTION: true

CLOCK_NET: io_clock_p2c
CLOCK_PERIOD: 20
CTS_OBSTRUCTION_AWARE: true

CTS_SINK_CLUSTERING_ENABLE: True
#CTS_SINK_CLUSTERING_SIZE: 8 # max is 8
#CTS_SINK_CLUSTERING_MAX_DIAMETER: 50

SIGNAL_WIRE_RC_LAYERS: [Metal2, Metal3, Metal4, Metal5]
CLOCK_WIRE_RC_LAYERS: [Metal2, Metal3, Metal4, Metal5]

# This is just for the clock pad to clock tree root buffer
#CTS_CLK_MAX_WIRE_LENGTH: 1000

# Floorplanning
FP_SIZING: absolute
DIE_AREA:  [   0.00,   0.00, 3600.00, 5000.00 ]
CORE_AREA: [ 362, 362, 3238, 4638 ]

FP_OBSTRUCTIONS:
- [444.96, 1068, 3238, 4638] # top area

PL_TARGET_DENSITY_PCT: 53 #43

PL_MAX_DISPLACEMENT_X: 1000
PL_MAX_DISPLACEMENT_Y: 300

# TopMetal2 obstructions for the logo
# Metal5 obstructions to prevent PDN from doing sth stupid between the SRAMs
PDN_OBSTRUCTIONS:
 - [TopMetal2, 450, 450, 900, 900]

ROUTING_OBSTRUCTIONS:
 - [TopMetal2, 450, 450, 900, 900]

# Don't insert buffers between eFPGA and SRAMs
RSZ_DONT_TOUCH_RX: "fabric_wrapper.fabric_.ram.*"

# Time driven placement ignores don't touch directives
# Therefore only enable routability driven
PL_TIME_DRIVEN: False
PL_ROUTABILITY_DRIVEN: True

#PL_ROUTABILITY_OVERFLOW_THRESHOLD: 0.2

# PDN
PDN_CFG: dir::pdn_cfg.tcl

PDN_CORE_RING_VWIDTH: 15
PDN_CORE_RING_HWIDTH: 15

PDN_VPITCH: 50
PDN_HPITCH: 50

PDN_VWIDTH: 3.5
PDN_HWIDTH: 3.5

# Because we have multiple power pads for one power domain
MAGIC_EXT_UNIQUE: notopports

PAD_SOUTH: [
    # Clock and reset
    sg13g2_IOPad_io_clock,
    sg13g2_IOPad_io_reset,

    # Flash
    "sg13g2_IOPad_io_flash_clk",
    "sg13g2_IOPad_io_flash_cs_n",
    "sg13g2_IOPad_flash\\[0\\].sg13g2_IOPad_io_flash_io",
    "sg13g2_IOPad_flash\\[1\\].sg13g2_IOPad_io_flash_io",
    "sg13g2_IOPad_flash\\[2\\].sg13g2_IOPad_io_flash_io",
    "sg13g2_IOPad_flash\\[3\\].sg13g2_IOPad_io_flash_io",

    # PSRAM
    "sg13g2_IOPad_io_psram_clk",
    "sg13g2_IOPad_io_psram_cs_n",
    "sg13g2_IOPad_psram\\[0\\].sg13g2_IOPad_io_psram_io",
    "sg13g2_IOPad_psram\\[1\\].sg13g2_IOPad_io_psram_io",
    "sg13g2_IOPad_psram\\[2\\].sg13g2_IOPad_io_psram_io",
    "sg13g2_IOPad_psram\\[3\\].sg13g2_IOPad_io_psram_io",

    # UART
    sg13g2_IOPad_io_ser_rx,
    sg13g2_IOPad_io_ser_tx
]

PAD_EAST: [
    sg13g2_IOPadIOVdd_east,
    sg13g2_IOPadIOVss_east,
        
    # Misc
    sg13g2_IOPad_io_fpga_mode,
    sg13g2_IOPad_io_fetch_enable,
    sg13g2_IOPad_io_config_busy,
    sg13g2_IOPad_io_core_sleep,
        
    "sg13g2_IOPad\\[0\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[1\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[2\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[3\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[4\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[5\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[6\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[7\\].sg13g2_IOPad_io_gpio",
    sg13g2_IOPadVss_east,
    sg13g2_IOPadVdd_east
]

PAD_NORTH: [
    "sg13g2_IOPad\\[23\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[22\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[21\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[20\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[19\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[18\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[17\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[16\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[15\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[14\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[13\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[12\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[11\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[10\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[9\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[8\\].sg13g2_IOPad_io_gpio"
]

PAD_WEST: [
    sg13g2_IOPadVdd_west,
    sg13g2_IOPadVss_west,

    "sg13g2_IOPad\\[31\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[30\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[29\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[28\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[27\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[26\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[25\\].sg13g2_IOPad_io_gpio",
    "sg13g2_IOPad\\[24\\].sg13g2_IOPad_io_gpio",
        
    # FPGA config
    "sg13g2_IOPad_io_fpga_sclk",
    "sg13g2_IOPad_io_fpga_cs_n",
    "sg13g2_IOPad_io_fpga_mosi",
    "sg13g2_IOPad_io_fpga_miso",
        
    sg13g2_IOPadIOVss_west,
    sg13g2_IOPadIOVdd_west
]

FP_MACRO_HORIZONTAL_HALO: 5
FP_MACRO_VERTICAL_HALO: 5

MACROS:
  
  # We can't add the logo as a macro, as otherwise
  # there will be an obstruction for stdcell placement
  #greyhound_logo:
  #  gds:
  #    - dir::logo/greyhound/greyhound_logo_drawing.gds
  #  lef:
  #    - dir::logo/greyhound/greyhound_logo.lef
  #  nl:
  #    - dir::logo/greyhound/greyhound_logo.v
  #  instances: 
  #    i_greyhound_logo:
  #      location: [450, 450]
  #      orientation: N

  eFPGA:
    gds:
      - dir::ip/fabric/macro/ihp-sg13g2/gds/eFPGA.gds
    lef:
      - dir::ip/fabric/macro/ihp-sg13g2/lef/eFPGA.lef
    nl:
      - dir::ip/fabric/macro/ihp-sg13g2/nl/eFPGA.nl.v
    spef:
      "nom_*":
        - dir::ip/fabric/macro/ihp-sg13g2/spef/nom/eFPGA.nom.spef
    instances: 
      i_greyhound_ihp.fabric_wrapper.eFPGA:
        # Width should be multiple of 0.48 (Metal2 pitch)
        # Height should be multiple of 0.42 (Metal3 pitch)
        location: [444.96, 1071]
        orientation: N
    
  RM_IHPSG13_1P_1024x32_c2_bm_bist:
    gds:
      - dir::ip/RM_IHPSG13_1P_1024x32_c2_bm_bist/gds/RM_IHPSG13_1P_1024x32_c2_bm_bist.gds
    lef:
      - dir::ip/RM_IHPSG13_1P_1024x32_c2_bm_bist/lef/RM_IHPSG13_1P_1024x32_c2_bm_bist.lef
    nl:
      - dir::ip/RM_IHPSG13_1P_1024x32_c2_bm_bist/verilog/RM_IHPSG13_1P_1024x32_c2_bm_bist.v
    lib:
      "nom_typ_1p20V_25C":
        - dir::ip/RM_IHPSG13_1P_1024x32_c2_bm_bist/lib/RM_IHPSG13_1P_1024x32_c2_bm_bist_typ_1p20V_25C.lib
      "nom_fast_1p32V_m40C":
        - dir::ip/RM_IHPSG13_1P_1024x32_c2_bm_bist/lib/RM_IHPSG13_1P_1024x32_c2_bm_bist_fast_1p32V_m55C.lib
      "nom_slow_1p08V_125C":
        - dir::ip/RM_IHPSG13_1P_1024x32_c2_bm_bist/lib/RM_IHPSG13_1P_1024x32_c2_bm_bist_slow_1p08V_125C.lib
    instances:
      i_greyhound_ihp.fabric_wrapper.sram0:
        location: [2861.5, 2416.50]
        orientation: E
      i_greyhound_ihp.fabric_wrapper.sram1:
        location: [2861.5, 1968.83]
        orientation: E
      i_greyhound_ihp.fabric_wrapper.sram2:
        location: [2861.5, 1521.15]
        orientation: E
      i_greyhound_ihp.fabric_wrapper.sram3:
        location: [2861.5, 1073.48]
        orientation: E

      i_greyhound_ihp.i_soc_sram0:
        location: [2820.96, 358.9]
        orientation: S

      i_greyhound_ihp.i_soc_sram1:
        location: [2820.96, 733.38]
        orientation: FN

  RM_IHPSG13_2P_1024x16_c2_bm_bist:
    gds:
      - dir::ip/RM_IHPSG13_2P_1024x16_c2_bm_bist/gds/RM_IHPSG13_2P_1024x16_c2_bm_bist.gds
    lef:
      - dir::ip/RM_IHPSG13_2P_1024x16_c2_bm_bist/lef/RM_IHPSG13_2P_1024x16_c2_bm_bist.lef
    nl:
      - dir::ip/RM_IHPSG13_2P_1024x16_c2_bm_bist/verilog/RM_IHPSG13_2P_1024x16_c2_bm_bist.v
    lib:
      "nom_typ_1p20V_25C":
        - dir::ip/RM_IHPSG13_2P_1024x16_c2_bm_bist/lib/RM_IHPSG13_2P_1024x16_c2_bm_bist_typ_1p20V_25C.lib
      "nom_fast_1p32V_m40C":
        - dir::ip/RM_IHPSG13_2P_1024x16_c2_bm_bist/lib/RM_IHPSG13_2P_1024x16_c2_bm_bist_fast_1p32V_m55C.lib
      "nom_slow_1p08V_125C":
        - dir::ip/RM_IHPSG13_2P_1024x16_c2_bm_bist/lib/RM_IHPSG13_2P_1024x16_c2_bm_bist_slow_1p08V_125C.lib
    instances:
      i_greyhound_ihp.fabric_wrapper.bram0:
        location: [2861.5, 4207.20]
        orientation: E
      i_greyhound_ihp.fabric_wrapper.bram1:
        location: [2861.5, 3759.53]
        orientation: E
      i_greyhound_ihp.fabric_wrapper.bram2:
        location: [2861.5, 3311.85]
        orientation: E
      i_greyhound_ihp.fabric_wrapper.bram3:
        location: [2861.5, 2864.18]
        orientation: E

PDN_MACRO_CONNECTIONS:
  - "i_greyhound_ihp.fabric_wrapper.eFPGA VDD VSS VPWR VGND"
  - "i_greyhound_ihp.fabric_wrapper.sram0 VDD VSS VDD! VSS!"
  - "i_greyhound_ihp.fabric_wrapper.sram0 VDD VSS VDDARRAY! VSS!"
  - "i_greyhound_ihp.fabric_wrapper.sram1 VDD VSS VDD! VSS!"
  - "i_greyhound_ihp.fabric_wrapper.sram1 VDD VSS VDDARRAY! VSS!"
  - "i_greyhound_ihp.fabric_wrapper.sram2 VDD VSS VDD! VSS!"
  - "i_greyhound_ihp.fabric_wrapper.sram2 VDD VSS VDDARRAY! VSS!"
  - "i_greyhound_ihp.fabric_wrapper.sram3 VDD VSS VDD! VSS!"
  - "i_greyhound_ihp.fabric_wrapper.sram3 VDD VSS VDDARRAY! VSS!"
  - "i_greyhound_ihp.fabric_wrapper.bram0 VDD VSS VDD! VSS!"
  - "i_greyhound_ihp.fabric_wrapper.bram0 VDD VSS VDDARRAY! VSS!"
  - "i_greyhound_ihp.fabric_wrapper.bram1 VDD VSS VDD! VSS!"
  - "i_greyhound_ihp.fabric_wrapper.bram1 VDD VSS VDDARRAY! VSS!"
  - "i_greyhound_ihp.fabric_wrapper.bram2 VDD VSS VDD! VSS!"
  - "i_greyhound_ihp.fabric_wrapper.bram2 VDD VSS VDDARRAY! VSS!"
  - "i_greyhound_ihp.fabric_wrapper.bram3 VDD VSS VDD! VSS!"
  - "i_greyhound_ihp.fabric_wrapper.bram3 VDD VSS VDDARRAY! VSS!"
  - "i_greyhound_ihp.i_soc_sram0 VDD VSS VDD! VSS!"
  - "i_greyhound_ihp.i_soc_sram0 VDD VSS VDDARRAY! VSS!"
  - "i_greyhound_ihp.i_soc_sram1 VDD VSS VDD! VSS!"
  - "i_greyhound_ihp.i_soc_sram1 VDD VSS VDDARRAY! VSS!"

# clk_buf16 > clk_bu16 = 0.07ns
# clk_buf1 > clk_buf1 = 0.027ns
#INSERT_ECO_BUFFERS:
#  # Cache (delay for ~1.382ns)
#- target: clkbuf_regs_0_clk_core/X
#  buffer: sg13g2_buf_1
#- target: clkbuf_regs_0_clk_core/X
#  buffer: sg13g2_buf_1
#- target: clkbuf_regs_0_clk_core/X
#  buffer: sg13g2_buf_1
#- target: clkbuf_regs_0_clk_core/X
#  buffer: sg13g2_buf_1
#- target: clkbuf_regs_0_clk_core/X
#  buffer: sg13g2_buf_1
#- target: clkbuf_regs_0_clk_core/X
#  buffer: sg13g2_buf_1
#- target: clkbuf_regs_0_clk_core/X
#  buffer: sg13g2_buf_1
#- target: clkbuf_regs_0_clk_core/X
#  buffer: sg13g2_buf_1
#- target: clkbuf_regs_0_clk_core/X
#  buffer: sg13g2_buf_1
#- target: clkbuf_regs_0_clk_core/X
#  buffer: sg13g2_buf_1
#- target: clkbuf_regs_0_clk_core/X
#  buffer: sg13g2_buf_1
#- target: clkbuf_regs_0_clk_core/X
#  buffer: sg13g2_buf_1
#- target: clkbuf_regs_0_clk_core/X
#  buffer: sg13g2_buf_1
#- target: clkbuf_regs_0_clk_core/X
#  buffer: sg13g2_buf_16
#  # UART (delay for ~1.422ns)
#- target: i_greyhound_ihp.i_greyhound_soc/i_EF_UART_AHBL.clk_gate_cell.clk_gate/GCLK
#  buffer: sg13g2_buf_1
#- target: i_greyhound_ihp.i_greyhound_soc/i_EF_UART_AHBL.clk_gate_cell.clk_gate/GCLK
#  buffer: sg13g2_buf_1
#- target: i_greyhound_ihp.i_greyhound_soc/i_EF_UART_AHBL.clk_gate_cell.clk_gate/GCLK
#  buffer: sg13g2_buf_1
#- target: i_greyhound_ihp.i_greyhound_soc/i_EF_UART_AHBL.clk_gate_cell.clk_gate/GCLK
#  buffer: sg13g2_buf_1
#- target: i_greyhound_ihp.i_greyhound_soc/i_EF_UART_AHBL.clk_gate_cell.clk_gate/GCLK
#  buffer: sg13g2_buf_1
#- target: i_greyhound_ihp.i_greyhound_soc/i_EF_UART_AHBL.clk_gate_cell.clk_gate/GCLK
#  buffer: sg13g2_buf_1
#- target: i_greyhound_ihp.i_greyhound_soc/i_EF_UART_AHBL.clk_gate_cell.clk_gate/GCLK
#  buffer: sg13g2_buf_1
#- target: i_greyhound_ihp.i_greyhound_soc/i_EF_UART_AHBL.clk_gate_cell.clk_gate/GCLK
#  buffer: sg13g2_buf_1
#- target: i_greyhound_ihp.i_greyhound_soc/i_EF_UART_AHBL.clk_gate_cell.clk_gate/GCLK
#  buffer: sg13g2_buf_1
#- target: i_greyhound_ihp.i_greyhound_soc/i_EF_UART_AHBL.clk_gate_cell.clk_gate/GCLK
#  buffer: sg13g2_buf_1
#- target: i_greyhound_ihp.i_greyhound_soc/i_EF_UART_AHBL.clk_gate_cell.clk_gate/GCLK
#  buffer: sg13g2_buf_1
#- target: i_greyhound_ihp.i_greyhound_soc/i_EF_UART_AHBL.clk_gate_cell.clk_gate/GCLK
#  buffer: sg13g2_buf_1
#- target: i_greyhound_ihp.i_greyhound_soc/i_EF_UART_AHBL.clk_gate_cell.clk_gate/GCLK
#  buffer: sg13g2_buf_1
#- target: i_greyhound_ihp.i_greyhound_soc/i_EF_UART_AHBL.clk_gate_cell.clk_gate/GCLK
#  buffer: sg13g2_buf_1
#- target: i_greyhound_ihp.i_greyhound_soc/i_EF_UART_AHBL.clk_gate_cell.clk_gate/GCLK
#  buffer: sg13g2_buf_1
#  # CV32E40X (delay for ~1.013ns)
#- target: i_greyhound_ihp.i_greyhound_soc/cv32e40x_core/sleep_unit_i.core_clock_gate_i.clk_gate/GCLK
#  buffer: sg13g2_buf_1
#- target: i_greyhound_ihp.i_greyhound_soc/cv32e40x_core/sleep_unit_i.core_clock_gate_i.clk_gate/GCLK
#  buffer: sg13g2_buf_1
#- target: i_greyhound_ihp.i_greyhound_soc/cv32e40x_core/sleep_unit_i.core_clock_gate_i.clk_gate/GCLK
#  buffer: sg13g2_buf_1
#- target: i_greyhound_ihp.i_greyhound_soc/cv32e40x_core/sleep_unit_i.core_clock_gate_i.clk_gate/GCLK
#  buffer: sg13g2_buf_1
#- target: i_greyhound_ihp.i_greyhound_soc/cv32e40x_core/sleep_unit_i.core_clock_gate_i.clk_gate/GCLK
#  buffer: sg13g2_buf_1
#- target: i_greyhound_ihp.i_greyhound_soc/cv32e40x_core/sleep_unit_i.core_clock_gate_i.clk_gate/GCLK
#  buffer: sg13g2_buf_1
#- target: i_greyhound_ihp.i_greyhound_soc/cv32e40x_core/sleep_unit_i.core_clock_gate_i.clk_gate/GCLK
#  buffer: sg13g2_buf_1
#- target: i_greyhound_ihp.i_greyhound_soc/cv32e40x_core/sleep_unit_i.core_clock_gate_i.clk_gate/GCLK
#  buffer: sg13g2_buf_1
#- target: i_greyhound_ihp.i_greyhound_soc/cv32e40x_core/sleep_unit_i.core_clock_gate_i.clk_gate/GCLK
#  buffer: sg13g2_buf_1
#- target: i_greyhound_ihp.i_greyhound_soc/cv32e40x_core/sleep_unit_i.core_clock_gate_i.clk_gate/GCLK
#  buffer: sg13g2_buf_1

DIODE_CELL: sg13g2_antennanp/A

INSERT_ECO_DIODES:
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y1_A_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y2_A_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y3_A_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y4_A_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y5_A_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y6_A_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y7_A_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y8_A_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y9_A_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y10_A_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y11_A_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y12_A_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y13_A_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y14_A_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y15_A_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y16_A_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y1_B_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y2_B_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y3_B_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y4_B_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y5_B_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y6_B_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y7_B_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y8_B_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y9_B_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y10_B_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y11_B_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y12_B_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y13_B_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y14_B_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y15_B_O_top
- target: i_greyhound_ihp.fabric_wrapper.eFPGA/Tile_X0Y16_B_O_top

# TODO CONFIGURED_TOP