From 87c5a78e5c5136285e573f2ad486ac84f4bee783 Mon Sep 17 00:00:00 2001 From: Satya Durga Srinivasu Prabhala Date: Mon, 11 Jul 2016 13:03:22 -0700 Subject: [PATCH 1/4] ARM: dts: msm: set rcu_expedited for msm chisets While working on PCMark Photo Editing regression, found that binder transactions sometimes take really long time 70+ms. The reason for these long durations was cgroup write calling percpu_down_write, which in turn calls synchronize_rcu. This issue is very generic and impacts multiple real-world use-cases involving all binder transactions. - All the launch applications also show it. - Systrace below is captured during launch of helloworld application. Systrace clearly shows the regression: Thread of interest: 562 Binder:528_1-562 ( 528) [000] ...1 57.877862: \ tracing_mark_write: B|528|Write Binder:528_1-562 ( 528) [000] .... 57.877905: \ __cgroup_procs_write.isra.30: percpu_down_write --> begin Binder:528_1-562 ( 528) [003] .... 57.926479: \ __cgroup_procs_write.isra.30: percpu_down_write --> end To mitigate these performance issues, set rcu_expedited to use expedited grace-period primitives. CRs-Fixed: 1025554 Change-Id: I1a6e694591f41d6c3449e3f3d976650df93c5645 Signed-off-by: Satya Durga Srinivasu Prabhala --- arch/arm/boot/dts/qcom/msm8996.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/msm8996.dtsi b/arch/arm/boot/dts/qcom/msm8996.dtsi index 742e21c92ad5..df093b4a752b 100755 --- a/arch/arm/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996.dtsi @@ -21,7 +21,7 @@ interrupt-parent = <&intc>; chosen { - bootargs = "sched_enable_hmp=1 sched_enable_power_aware=1 app_setting.use_32bit_app_setting=1"; + bootargs = "sched_enable_hmp=1 sched_enable_power_aware=1 app_setting.use_32bit_app_setting=1 rcupdate.rcu_expedited=1"; }; aliases { From 209bf511c63c8f3da28761728f92c582774ef124 Mon Sep 17 00:00:00 2001 From: "Angelo G. Del Regno" Date: Tue, 19 Dec 2017 17:19:48 +0100 Subject: [PATCH 2/4] arm: DT: msm8996-regulator: Fix bad s11 VCORE constraints for HW conf The HW can be configured with hard limits: those weren't being respected in the DT configuration and, whenever we tried to set a voltage that was lower than the HW limits, we were getting a silent failure, producing a lot of unneeded power consumption. --- arch/arm/boot/dts/qcom/msm8996-regulator.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/msm8996-regulator.dtsi b/arch/arm/boot/dts/qcom/msm8996-regulator.dtsi index 41d04e4c9632..b09729e81940 100644 --- a/arch/arm/boot/dts/qcom/msm8996-regulator.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996-regulator.dtsi @@ -513,7 +513,7 @@ compatible = "qcom,spm-regulator"; reg = <0x3200 0x100>; regulator-name = "pm8994_s11"; - regulator-min-microvolt = <470000>; + regulator-min-microvolt = <475000>; regulator-max-microvolt = <1140000>; qcom,max-voltage-step = <150000>; qcom,cpu-num = <0>; @@ -521,7 +521,7 @@ pm8994_s11_limit: avs-limit-regulator { regulator-name = "pm8994_s11_avs_limit"; - regulator-min-microvolt = <470000>; + regulator-min-microvolt = <475000>; regulator-max-microvolt = <1140000>; }; }; From 438c335ecabda541123aa5382d0ecbdc39387321 Mon Sep 17 00:00:00 2001 From: "Angelo G. Del Regno" Date: Sat, 24 Jun 2017 18:17:07 +0200 Subject: [PATCH 3/4] arm: DT: MSM8996: Add efficiency parameter to each SoC CPU This is not completely necessary but, on k4.4, it allows better scheduling. --- arch/arm/boot/dts/qcom/msm8996.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/qcom/msm8996.dtsi b/arch/arm/boot/dts/qcom/msm8996.dtsi index df093b4a752b..e98e84a7d79a 100755 --- a/arch/arm/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996.dtsi @@ -61,6 +61,7 @@ reg = <0x0 0x0>; qcom,limits-info = <&mitigation_profile0>; enable-method = "psci"; + efficiency = <1024>; qcom,ea = <&ea0>; next-level-cache = <&L2_0>; L2_0: l2-cache { @@ -83,6 +84,7 @@ reg = <0x0 0x1>; qcom,limits-info = <&mitigation_profile1>; enable-method = "psci"; + efficiency = <1024>; qcom,ea = <&ea1>; next-level-cache = <&L2_0>; L1_D_1: l1-dcache { @@ -100,6 +102,7 @@ reg = <0x0 0x100>; qcom,limits-info = <&mitigation_profile2>; enable-method = "psci"; + efficiency = <1536>; qcom,ea = <&ea2>; next-level-cache = <&L2_1>; L2_1: l2-cache { @@ -122,6 +125,7 @@ reg = <0x0 0x101>; enable-method = "psci"; qcom,limits-info = <&mitigation_profile3>; + efficiency = <1536>; qcom,ea = <&ea3>; next-level-cache = <&L2_1>; L1_D_101: l1-dcache { From 1a42d2848cff5afe0d1ebd2c42dddafa0400f0a3 Mon Sep 17 00:00:00 2001 From: BrateloSlava Date: Sat, 10 Feb 2018 21:09:51 +0200 Subject: [PATCH 4/4] dts: set 27MHz as default GPU idle freq More power saving --- arch/arm/boot/dts/qcom/msm8996-v3.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom/msm8996-v3.dtsi b/arch/arm/boot/dts/qcom/msm8996-v3.dtsi index f9ca5b12bda8..b29e7afbec78 100644 --- a/arch/arm/boot/dts/qcom/msm8996-v3.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996-v3.dtsi @@ -154,7 +154,7 @@ qcom,speed-bin = <0>; - qcom,initial-pwrlevel = <6>; + qcom,initial-pwrlevel = <7>; qcom,gpu-pwrlevel@0 { reg = <0>; @@ -227,7 +227,7 @@ qcom,speed-bin = <1>; - qcom,initial-pwrlevel = <4>; + qcom,initial-pwrlevel = <5>; qcom,gpu-pwrlevel@0 { reg = <0>; @@ -284,7 +284,7 @@ qcom,speed-bin = <2>; - qcom,initial-pwrlevel = <5>; + qcom,initial-pwrlevel = <6>; qcom,gpu-pwrlevel@0 { reg = <0>; @@ -350,7 +350,7 @@ qcom,speed-bin = <3>; - qcom,initial-pwrlevel = <5>; + qcom,initial-pwrlevel = <7>; qcom,gpu-pwrlevel@0 { reg = <0>;