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Update sgemm.cpp
1 parent eb29b03 commit f409a78

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Lines changed: 9 additions & 79 deletions

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llamafile/sgemm.cpp

Lines changed: 9 additions & 79 deletions
Original file line numberDiff line numberDiff line change
@@ -25,15 +25,10 @@
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// #include <cpuid.h>
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// #include <libc/sysv/consts/hwcap.h>
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#include <stdio.h>
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#include <sys/auxv.h>
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#include <cassert>
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// #include "llamafile.h"
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// ARM64-specific headers and constants
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#ifdef __aarch64__
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#include <sys/auxv.h>
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#include <asm/hwcap.h>
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#endif
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static const struct GemmFuncs {
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bool (*sgemm)(long, long, long, const void*, long, const void*, long, void*, long, int, int, int, int, int, int, int);
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bool (*mixmul)(const struct ggml_compute_params*, const struct ggml_tensor*, const struct ggml_tensor*, const struct ggml_tensor*, struct ggml_tensor*);
@@ -42,7 +37,7 @@ static const struct GemmFuncs {
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// typeof(llamafile_mixmul)* mixmul;
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// typeof(llamafile_mixmul_iqk)* iqk_mixmul = iqk_mul_mat_moe_unsupported;
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GemmFuncs() {
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#if defined(__x86_64__) || defined(_M_X64)
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//#if defined(__x86_64__) || defined(_M_X64)
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// if (X86_HAVE(AVX)) {
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// if (X86_HAVE(FMA)) {
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// if (X86_HAVE(AVX2)) {
@@ -95,83 +90,18 @@ static const struct GemmFuncs {
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// mixmul = llamafile_mixmul_unsupported;
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// }
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#if defined(__AVX__)
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#if defined(__FMA__) || (defined(_MSC_VER) && (defined(__AVX2__) || defined(__AVX512F__)))
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#if defined(__AVX2__)
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#if defined(__AVX512F__)
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#if defined(__AVX512VL__) && defined(__AVX512BW__) && defined(__AVX512DQ__) && defined(__AVX512VNNI__) && defined(__AVX512BF16__)
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// AMD Zen4+ (2023-)
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sgemm = llamafile_sgemm_amd_zen4;
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mixmul = llamafile_mixmul_amd_zen4;
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iqk_mixmul = iqk_mul_mat_moe_zen4;
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#else
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// Intel Xeon Skylake+ (2015-)
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sgemm = llamafile_sgemm_amd_avx512f;
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mixmul = llamafile_mixmul_amd_avx512f;
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iqk_mixmul = iqk_mul_mat_moe;
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#endif
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#elif defined(__AVXVNNI__)
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// Intel Alderlake (2021-)
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sgemm = llamafile_sgemm_amd_avxvnni;
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mixmul = llamafile_mixmul_amd_avxvnni;
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iqk_mixmul = iqk_mul_mat_moe;
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#else
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// Intel Haswell/Broadwell/Skylake (2013-2020)
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// AMD Excavator (2015-2022)
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sgemm = llamafile_sgemm_amd_avx2;
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mixmul = llamafile_mixmul_amd_avx2;
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#if defined(__F16C__)
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iqk_mixmul = iqk_mul_mat_moe;
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#endif
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#endif
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#else
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// AMD Piledriver (2011-2014)
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sgemm = llamafile_sgemm_amd_fma;
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mixmul = llamafile_mixmul_amd_fma;
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#if defined(__F16C__)
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iqk_mixmul = iqk_mul_mat_moe;
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#endif
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#endif
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#else
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// Intel Sandybridge/Ivybridge (2010-2012)
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// AMD Bulldozer (2011)
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sgemm = llamafile_sgemm_amd_avx;
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mixmul = llamafile_mixmul_amd_avx;
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#endif
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#else
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// AMD K8/Barcelona (2003-2010)
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// Intel Core/Nehalem (2006-2009)
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sgemm = llamafile_sgemm_unsupported;
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mixmul = llamafile_mixmul_unsupported;
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#endif
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148-
#elif defined(__aarch64__)
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// ARM64 hardware capability detection
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long hwcap = 0;
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#ifdef __linux__
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hwcap = getauxval(AT_HWCAP);
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if ((hwcap & HWCAP_FPHP) && // fp16 scalar isa (ID_AA64PFR0_EL1.FP == 1)
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(hwcap & HWCAP_ASIMDHP) && // fp16 vector isa (ID_AA64PFR0_EL1.AdvSIMD == 1)
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(hwcap & HWCAP_ASIMDDP)) { // dotprod isa (ID_AA64ISAR0_EL1.DP == 1)
94+
//#elif defined(__aarch64__)
95+
//long hwcap = getauxval(AT_HWCAP);
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//if ((hwcap & HWCAP_FPHP) && // fp16 scalar isa (ID_AA64PFR0_EL1.FP == 1)
97+
// (hwcap & HWCAP_ASIMDHP) && // fp16 vector isa (ID_AA64PFR0_EL1.AdvSIMD == 1)
98+
// (hwcap & HWCAP_ASIMDDP)) { // dotprod isa (ID_AA64ISAR0_EL1.DP == 1)
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// e.g. Apple M1, Raspberry Pi 5
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sgemm = llamafile_sgemm_arm82;
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mixmul = llamafile_mixmul_arm82;
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iqk_mixmul = iqk_mul_mat_moe_arm82;
160-
} else {
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// ARM64 baseline ISA
162-
sgemm = llamafile_sgemm_arm80;
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mixmul = llamafile_mixmul_arm80;
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}
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#else
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// Non-Linux ARM64 systems (e.g., macOS)
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// Use baseline ARM64 implementation
168-
sgemm = llamafile_sgemm_arm80;
169-
mixmul = llamafile_mixmul_arm80;
170-
#endif
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#else
172-
sgemm = llamafile_sgemm_unsupported;
173-
mixmul = llamafile_mixmul_unsupported;
174-
#endif
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104+
//#endif
175105
}
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} funcs;
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