aarch64: Fix JIT for PIE builds

On aarch64, jitted code ends up segfaulting on PIE HHVM builds.
Running a debug build pointed to `makeTarget32` receiving a 64-bit
pointer instead of the expected 32-bit pointer, so rework affected
usages to operate on 64-bit pointers and registers instead.

x86 is not affected by this issue because it presumably makes
no equivalent assumption about pointer sizing.

Author: mszabo-wikia

hphp/runtime/vm/jit/smashable-instr-arm.cpp

@@ -69,7 +69,6 @@ TCA emitSmashableCall(CodeBlock& cb, CGMeta& meta, TCA target) {
   auto const the_start = cb.frontier();
   meta.smashableLocations.insert(the_start);
 
-  assertx((makeTarget32(target) & 3) == 0);
   addVeneer(meta, the_start, target);
   vixl::Label veneer_addr;
   a.bind(&veneer_addr);
@@ -87,7 +86,6 @@ TCA emitSmashableJmp(CodeBlock& cb, CGMeta& meta, TCA target) {
   auto const the_start = cb.frontier();
   meta.smashableLocations.insert(the_start);
 
-  assertx((makeTarget32(target) & 3) == 0);
   addVeneer(meta, the_start, target);
   vixl::Label veneer_addr;
   a.bind(&veneer_addr);
@@ -106,7 +104,6 @@ TCA emitSmashableJcc(CodeBlock& cb, CGMeta& meta, TCA target,
   auto const the_start = cb.frontier();
   meta.smashableLocations.insert(the_start);
 
-  assertx((makeTarget32(target) & 3) == 0);
   addVeneer(meta, the_start, target);
   vixl::Label veneer_addr;
   a.bind(&veneer_addr);
@@ -148,7 +145,7 @@ bool isVeneer(vixl::Instruction* ldr) {
   auto const rd = ldr->Rd();
 
   return (ldr->IsLoadLiteral() &&
-          ldr->Mask(LoadLiteralMask) == LDR_w_lit &&
+          ldr->Mask(LoadLiteralMask) == LDR_x_lit &&
           br->Mask(UnconditionalBranchToRegisterMask) == BR &&
           br->Rn() == rd);
 }
@@ -206,7 +203,7 @@ void smashCall(TCA inst, TCA target) {
 
   auto const bl = Instruction::Cast(inst);
   auto const ldr = bl->ImmPCOffsetTarget();
-  patchTarget32(ldr->LiteralAddress(), target);
+  patchTarget64(ldr->LiteralAddress(), target);
 
   // If the target can be reached through a direct call, then patch the original
   // call.  Notice that this optimization prevents a debugger guard from being
@@ -247,7 +244,7 @@ void smashJmp(TCA inst, TCA target) {
 
   auto const b = Instruction::Cast(inst);
   auto const ldr = b->ImmPCOffsetTarget();
-  patchTarget32(ldr->LiteralAddress(), target);
+  patchTarget64(ldr->LiteralAddress(), target);
 
   // If the target can be reached through a direct jump, then patch the original
   // jump.  Notice that this optimization prevents a debugger guard from being
@@ -286,7 +283,7 @@ void smashJcc(TCA inst, TCA target) {
 
   auto const b = Instruction::Cast(inst);
   auto const ldr = b->ImmPCOffsetTarget();
-  patchTarget32(ldr->LiteralAddress(), target);
+  patchTarget64(ldr->LiteralAddress(), target);
 
   // If the target can be reached through a direct branch, then patch the
   // original branch.  Notice that this optimization prevents a debugger guard

hphp/runtime/vm/jit/vasm-arm.cpp

@@ -528,9 +528,9 @@ void Vgen::emitVeneers(Venv& env) {
     MacroAssembler av{*cb};
     vixl::Label target_data;
     meta.addressImmediates.insert(vaddr);
-    poolLiteral(*cb, meta, (uint64_t)makeTarget32(veneer.target), 32, true);
+    poolLiteral(*cb, meta, (uint64_t)veneer.target, 64, true);
     av.bind(&target_data);
-    av.Ldr(rAsm_w, &target_data);
+    av.Ldr(rAsm, &target_data);
     av.Br(rAsm);
 
     // Update the veneer source instruction to jump/call the veneer.
@@ -681,17 +681,17 @@ void Vgen::processVveneers(Venv& env) {
 
 void Vgen::patch(Venv& env) {
   // Patch the 32 bit target of the LDR
-  auto patch = [&env](TCA instr, TCA target) {
+  auto patch = [](TCA instr, TCA target) {
     // The LDR loading the address to branch to.
     auto ldr = Instruction::Cast(instr);
     auto const DEBUG_ONLY br = ldr->NextInstruction();
-    assertx(ldr->Mask(LoadLiteralMask) == LDR_w_lit &&
+    assertx(ldr->Mask(LoadLiteralMask) == LDR_x_lit &&
             br->Mask(UnconditionalBranchToRegisterMask) == BR &&
             ldr->Rd() == br->Rn());
     // The address the LDR loads.
     auto targetAddr = ldr->LiteralAddress();
     // Patch the 32 bit target following the LDR and BR
-    patchTarget32(targetAddr, target);
+    patchTarget64(targetAddr, target);
   };
 
   for (auto const& p : env.jmps) {
@@ -1067,10 +1067,10 @@ void Vgen::emit(const jcc& i) {
       recordAddressImmediate();
       a->B(&skip, vixl::InvertCondition(C(i.cc)));
       recordAddressImmediate();
-      poolLiteral(*env.cb, env.meta, (uint64_t)makeTarget32(a->frontier()),
-                  32, false);
+      poolLiteral(*env.cb, env.meta, (uint64_t)a->frontier(),
+                  64, false);
       a->bind(&data);  // This will be remmaped during the handleLiterals phase.
-      a->Ldr(rAsm_w, &data);
+      a->Ldr(rAsm, &data);
       a->Br(rAsm);
       a->bind(&skip);
     }
@@ -1095,9 +1095,9 @@ void Vgen::emit(const jmp& i) {
   // Emit a "far JMP" sequence for easy patching later.  Static relocation
   // might be able to simplify this (see optimizeFarJmp()).
   recordAddressImmediate();
-  poolLiteral(*env.cb, env.meta, (uint64_t)a->frontier(), 32, false);
+  poolLiteral(*env.cb, env.meta, (uint64_t)a->frontier(), 64, false);
   a->bind(&data); // This will be remapped during the handleLiterals phase.
-  a->Ldr(rAsm_w, &data);
+  a->Ldr(rAsm, &data);
   a->Br(rAsm);
 }
 
@@ -1107,9 +1107,9 @@ void Vgen::emit(const jmpi& i) {
   // Cannot use simple a->Mov() since such a sequence cannot be
   // adjusted while live following a relocation.
   recordAddressImmediate();
-  poolLiteral(*env.cb, env.meta, (uint64_t)i.target, 32, false);
+  poolLiteral(*env.cb, env.meta, (uint64_t)i.target, 64, false);
   a->bind(&data); // This will be remapped during the handleLiterals phase.
-  a->Ldr(rAsm_w, &data);
+  a->Ldr(rAsm, &data);
   a->Br(rAsm);
 }