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[BH-1866] Port new eMMC driver to Pure
This port updates only eMMC driver and a few files from new FSL. This change should solve issue with init eMMC memory.
1 parent 56d563a commit f682474

29 files changed

+10910
-5164
lines changed

‎hal/include/hal/emmc.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
#pragma once
22

3+
#include <drivers/sdmmc/fsl_mmc.h>
34

45
// Forward decl
56
struct _mmc_card;
@@ -11,7 +12,7 @@ void emmc_enable(void);
1112
/** Initialize emmc card subsystem
1213
* @return error code
1314
*/
14-
int emmc_init();
15+
status_t emmc_init();
1516

1617
/** Get emmc card from master driver
1718
* @return emmc card structure or null

‎hal/src/display/ED028TC1.c‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,8 @@ EinkInitialize(EinkBpp_e bpp)
6868
lpspi_master_config_t masterConfig;
6969
int i;
7070

71+
LPSPI_MasterGetDefaultConfig(&masterConfig);
72+
7173
/*Set clock source for LPSPI*/
7274
// CLOCK_SetMux(kCLOCK_LpspiMux, BOARD_EINK_LPSPI_CLOCK_SOURCE_SELECT);
7375
// CLOCK_SetDiv(kCLOCK_LpspiDiv, BOARD_EINK_LPSPI_CLOCK_SOURCE_DIVIDER);

‎hal/src/emmc.c‎

Lines changed: 122 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -1,50 +1,149 @@
11
#include <hal/emmc.h>
2-
#include <drivers/sdmmc/fsl_mmc.h>
3-
#include <drivers/sdmmc/fsl_sdmmc_host.h>
2+
#include <boot/board.h>
3+
#include "MIMXRT1051.h"
44
#include <errno.h>
55
#include <stdbool.h>
66

7+
#include <drivers/fsl_iomuxc.h>
8+
#include <hal/delay.h>
9+
10+
11+
#define BOARD_SDMMC_MMC_HOST_SUPPORT_HS200_FREQ (180000000U)
12+
#define DMA_BUFFER_WORD_SIZE (1024U)
13+
#define USDHC_IRQ_PRIORITY (6U)
14+
15+
AT_NONCACHEABLE_SECTION_ALIGN(uint32_t s_sdmmc_hostDmaBuffer[DMA_BUFFER_WORD_SIZE], SDMMCHOST_DMA_DESCRIPTOR_BUFFER_ALIGN_SIZE);
16+
717
static mmc_card_t mmc_card;
18+
static sdmmchost_t mmc_host;
819
static bool init_ok;
920

10-
/** Enable the clocks in the emmc card
11-
* @return error
12-
*/
21+
static void emmc_pin_config(uint32_t freq);
22+
1323
void emmc_enable(void)
1424
{
15-
/* Configure USDHC clock source and divider */
16-
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 2); //bylo 2
17-
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); // CSCMR1 (17) 0 - PLL2_PFD2, 1 - PLL2_PFD0
25+
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 3);
26+
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); // 0 - PLL2_PFD2, 1 - PLL2_PFD0
1827
CLOCK_EnableClock(kCLOCK_Usdhc2);
1928
}
2029

21-
/** Initialize the EMMC card */
22-
int emmc_init(void)
30+
status_t emmc_init(void)
2331
{
24-
//config_emmc();
25-
/* Configure base eMMC parameters*/
2632
memset(&mmc_card, 0, sizeof(mmc_card));
33+
memset(&mmc_host, 0, sizeof(mmc_host));
34+
mmc_card.host = &mmc_host;
35+
36+
mmc_host.dmaDesBuffer = s_sdmmc_hostDmaBuffer;
37+
mmc_host.dmaDesBufferWordsNum = DMA_BUFFER_WORD_SIZE;
38+
mmc_host.enableCacheControl = kSDMMCHOST_CacheControlRWBuffer;
39+
#if defined SDmmc_host_ENABLE_CACHE_LINE_ALIGN_TRANSFER && SDmmc_host_ENABLE_CACHE_LINE_ALIGN_TRANSFER
40+
mmc_host.cacheAlignBuffer = s_sdmmcCacheLineAlignBuffer;
41+
mmc_host.cacheAlignBufferSize = BOARD_SDMMC_DATA_BUFFER_ALIGN_SIZE * 2U;
42+
#endif
2743

2844
mmc_card.busWidth = kMMC_DataBusWidth8bit;
29-
mmc_card.busTiming = /*kMMC_HighSpeed200Timing;*/ kMMC_HighSpeedTiming;
45+
mmc_card.busTiming = kMMC_HighSpeed200Timing;
3046
mmc_card.enablePreDefinedBlockCount = true;
31-
mmc_card.host.base = MMC_HOST_BASEADDR;
32-
mmc_card.host.sourceClock_Hz = MMC_HOST_CLK_FREQ;
47+
mmc_card.host->hostController.base = BOARD_MMC_HOST_BASEADDR;
48+
mmc_card.host->hostController.sourceClock_Hz = BOARD_MMC_HOST_CLK_FREQ;
49+
mmc_card.usrParam.ioStrength = emmc_pin_config;
50+
mmc_card.usrParam.maxFreq = BOARD_SDMMC_MMC_HOST_SUPPORT_HS200_FREQ;
51+
mmc_card.hostVoltageWindowVCCQ = kMMC_VoltageWindow120;
52+
mmc_card.hostVoltageWindowVCC = kMMC_VoltageWindow170to195;
3353
/* card detect type */
3454
#if defined DEMO_SDCARD_POWER_CTRL_FUNCTION_EXIST
3555
g_sd.usrParam.pwr = &s_sdCardPwrCtrl;
3656
#endif
37-
if (MMC_Init(&mmc_card) != kStatus_Success)
57+
58+
const status_t status = MMC_Init(&mmc_card);
59+
if (status == kStatus_Success) {
60+
init_ok = true;
61+
NVIC_SetPriority(USDHC2_IRQn, USDHC_IRQ_PRIORITY);
62+
return kStatus_Success;
63+
}
64+
65+
return status;
66+
}
67+
68+
static void emmc_pin_config(uint32_t freq)
69+
{
70+
uint32_t speed = 0U, strength = 0U;
71+
72+
if (freq <= 50000000)
73+
{
74+
speed = 0U;
75+
strength = 7U;
76+
}
77+
else if (freq <= 100000000)
78+
{
79+
speed = 2U;
80+
strength = 7U;
81+
}
82+
else
3883
{
39-
return -1;
84+
speed = 3U;
85+
strength = 7U;
4086
}
41-
init_ok = true;
42-
return 0;
87+
88+
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_05_USDHC2_CMD,
89+
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
90+
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
91+
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
92+
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
93+
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_04_USDHC2_CLK,
94+
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
95+
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
96+
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
97+
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0,
98+
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
99+
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
100+
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
101+
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
102+
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1,
103+
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
104+
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
105+
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
106+
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
107+
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2,
108+
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
109+
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
110+
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
111+
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
112+
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3,
113+
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
114+
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
115+
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
116+
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
117+
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4,
118+
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
119+
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
120+
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
121+
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
122+
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5,
123+
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
124+
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
125+
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
126+
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
127+
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6,
128+
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
129+
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
130+
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
131+
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
132+
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7,
133+
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
134+
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
135+
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
136+
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
43137
}
44138

45-
/* Retrive the mmc card object structure
46-
*/
47-
struct _mmc_card* emmc_card()
139+
struct _mmc_card* emmc_card(void)
48140
{
49-
return (init_ok)?(&mmc_card):(NULL);
141+
return init_ok ? &mmc_card : NULL;
50142
}
143+
144+
// Overwrite a weak function for getting msec
145+
uint32_t OSA_TimeGetMsec(void)
146+
{
147+
return get_jiffiess();
148+
}
149+

‎platform/CMSIS/MIMXRT1051_features.h‎

Lines changed: 16 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -556,13 +556,6 @@
556556
/* @brief TRNG has no TRNG_ACC bitfield. */
557557
#define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1)
558558

559-
/* USBHS module features */
560-
561-
/* @brief EHCI module instance count */
562-
#define FSL_FEATURE_USBHS_EHCI_COUNT (2)
563-
/* @brief Number of endpoints supported */
564-
#define FSL_FEATURE_USBHS_ENDPT_COUNT (8)
565-
566559
/* USDHC module features */
567560

568561
/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */
@@ -573,6 +566,22 @@
573566
#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1)
574567
/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */
575568
#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1)
569+
/* @brief USDHC has reset control */
570+
#define FSL_FEATURE_USDHC_HAS_RESET (0)
571+
/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */
572+
#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0)
573+
/* @brief If USDHC instance support 8 bit width */
574+
#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) \
575+
(((x) == USDHC1) ? (0) : \
576+
(((x) == USDHC2) ? (1) : (-1)))
577+
/* @brief If USDHC instance support HS400 mode */
578+
#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0)
579+
/* @brief If USDHC instance support 1v8 signal */
580+
#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1)
581+
/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */
582+
#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (0)
583+
/* @brief Has no VSELECT bit in VEND_SPEC register */
584+
#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (0)
576585

577586
/* XBARA module features */
578587

‎platform/CMSIS/fsl_device_registers.h‎

Lines changed: 4 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -1,37 +1,9 @@
11
/*
2-
* The Clear BSD License
32
* Copyright 2014-2016 Freescale Semiconductor, Inc.
4-
* Copyright 2016-2018 NXP
3+
* Copyright 2016-2019 NXP
54
* All rights reserved.
65
*
7-
* Redistribution and use in source and binary forms, with or without
8-
* modification, are permitted (subject to the limitations in the
9-
* disclaimer below) provided that the following conditions are met:
10-
*
11-
* * Redistributions of source code must retain the above copyright
12-
* notice, this list of conditions and the following disclaimer.
13-
*
14-
* * Redistributions in binary form must reproduce the above copyright
15-
* notice, this list of conditions and the following disclaimer in the
16-
* documentation and/or other materials provided with the distribution.
17-
*
18-
* * Neither the name of the copyright holder nor the names of its
19-
* contributors may be used to endorse or promote products derived from
20-
* this software without specific prior written permission.
21-
*
22-
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
23-
* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
24-
* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
25-
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
26-
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27-
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
28-
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29-
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30-
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31-
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32-
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33-
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34-
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6+
* SPDX-License-Identifier: BSD-3-Clause
357
*
368
*/
379

@@ -43,7 +15,8 @@
4315
*
4416
* The CPU macro should be declared in the project or makefile.
4517
*/
46-
#if (defined(CPU_MIMXRT1051CVJ5B) || defined(CPU_MIMXRT1051CVL5B) || defined(CPU_MIMXRT1051DVL6B))
18+
#if (defined(CPU_MIMXRT1051CVJ5B) || defined(CPU_MIMXRT1051CVL5B) || defined(CPU_MIMXRT1051DVJ6B) || \
19+
defined(CPU_MIMXRT1051DVL6B))
4720

4821
#define MIMXRT1051_SERIES
4922

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