Vending-Machine/VendMachine_tb.v at master · mzd95/Vending-Machine · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
module VendMachine_tb();
  reg clk, reset, enable, serialIn;
  reg [1:0] product;
  reg buy;
  wire [6:0] digit1, digit0;
  wire penny, nickle,dime, quarter;
  wire [9:0] diameter;
  wire error;
  wire [1:0] pro;
  wire [7:0] credit;

  VendMachine_B VB(clk, reset, enable, serialIn, product, buy, digit1, digit0, penny, nickle, dime, quarter, diameter, error, pro, credit);

  function [9:0] rando;
    input [9:0] min;
    input [9:0] max;
    rando = min + {$random} % (max-min);
  endfunction

  task write_bits;
    input [9:0] data;
    reg [4:0] i;
    for (i=0; i<10; i=i+1)
    begin
      @(posedge clk);
      serialIn <= data[9-i];
    end
  endtask

  covergroup myCoverGroup @(clk);
    PENNY : coverpoint penny;
    NICKLE : coverpoint nickle;
    DIME : coverpoint dime;
    QUARTER : coverpoint quarter;
    CREDIT : coverpoint credit {
                               bins zero = {[0:4]};
                               bins one = {[5:9]};
                               bins two = {[10:24]};
                               bins three = {[25:39]};
                               bins four = {[40:59]};
                               bins five = {[60:74]};
                               bins six = {[75:255]};
                               }
    ERROR : coverpoint error;
    PRO : coverpoint pro;
    CROSS_COVERAGE : cross PRO, ERROR;
  endgroup

  always #10 clk <= ~clk;

  initial begin
    myCoverGroup cg;
    cg = new();
    clk <= 1'b1;
    reset <= 1'b0;
    enable <= 1'b0;
    product <= 2'b00;
    buy <= 1'b0;
    #30
    reset <= 1'b1;
    #20
    enable <= 1'b1;
    #20
    write_bits(rando(10'b1011111010, 10'b1100000101));
    #20
    enable <= 1'b0;
    #60
    buy <= 1'b1;
    #20
    buy <= 1'b0;
    #80
    enable <= 1'b1;
    #20
    write_bits(rando(10'b1011110000, 10'b1011111010));
    #20
    enable <= 1'b0;
    #80
    enable <= 1'b1;
    #20
    write_bits(rando(10'b1011001100, 10'b1011010000));
    #20
    enable <= 1'b0;
    #80
    enable <= 1'b1;
    #20
    write_bits(rando(10'b1111010000, 10'b1111010111));
    #20
    enable <= 1'b0;
    product <= 2'b11;
    #20
    product <= 2'b01;
    #60
    buy <= 1'b1;
    #20
    buy <= 1'b0;
    #60
    product <= 2'b00;
    #60
    buy <= 1'b1;
    enable <= 1'b1;
    #20
    write_bits(rando(10'b1101010001,10'b1101011100));
    #20
    enable <= 1'b0;
    product <= 2'b11;
    #80
    buy <= 1'b1;
    #20
    buy <= 1'b0;
    #40
    enable <= 1'b1;
    #20
    write_bits(rando(10'b1011001100, 10'b1011010111));
    #20
    enable <= 1'b0;
    product <= 2'b10;
    #60
    buy <= 1'b1;
  end

endmodule