fixed freq_div_list

Author: rze

v10_prototype_version_2/20220109/config.py

@@ -136,70 +136,70 @@
 
 clk_div_list = array("I", [0 for _ in range(64)])
 
-clk_div_list[0] = 0b111100111110110101011100000000
-clk_div_list[1] = 0b111100111110110101011100000000
-clk_div_list[2] = 0b111100111110110101011100000000
-clk_div_list[3] = 0b111100111110110101011100000000
-clk_div_list[4] = 0b111100111110110101011100000000
-clk_div_list[5] = 0b111100111110110101011100000000
-clk_div_list[6] = 0b111100111110110101011100000000
-clk_div_list[7] = 0b111100111110110101011100000000
-clk_div_list[8] = 0b111100111110110101011100000000
-clk_div_list[9] = 0b111100111110110101011100000000
-clk_div_list[10] = 0b111100111110110101011100000000
-clk_div_list[11] = 0b111100111110110101011100000000
-clk_div_list[12] = 0b111100111110110101011100000000
-clk_div_list[13] = 0b111100111110110101011100000000
-clk_div_list[14] = 0b111100111110110101011100000000
-clk_div_list[15] = 0b111100111110110101011100000000
-clk_div_list[16] = 0b111100111110110101011100000000
-clk_div_list[17] = 0b110111110000100100101100000000
-clk_div_list[18] = 0b110011010110101101001000000000
-clk_div_list[19] = 0b101111100110000110110000000000
-clk_div_list[20] = 0b101100010110100101100000000000
-clk_div_list[21] = 0b101001100001010100000000000000
-clk_div_list[22] = 0b100111000001110011010100000000
-clk_div_list[23] = 0b100100110100100010001100000000
-clk_div_list[24] = 0b100010110110001110110000000000
-clk_div_list[25] = 0b100001000100110001110100000000
-clk_div_list[26] = 0b11111011110011100001000000000
-clk_div_list[27] = 0b11110000001011010111100000000
-clk_div_list[28] = 0b11100101100100111010100000000
-clk_div_list[29] = 0b11011011111000100111000000000
-clk_div_list[30] = 0b11010010111101110101100000000
-clk_div_list[31] = 0b11001010101111100011000000000
-clk_div_list[32] = 0b11000011001000110000100000000
-clk_div_list[33] = 0b1111100111000110101100000000
-clk_div_list[34] = 0b1011011110101000110000000000
-clk_div_list[35] = 0b1001000100111000000100000000
-clk_div_list[36] = 0b111100000010101110000000000
-clk_div_list[37] = 0b110011001011110001000000000
-clk_div_list[38] = 0b101100100110100110000000000
-clk_div_list[39] = 0b100111100001011001000000000
-clk_div_list[40] = 0b100011011110101011100000000
-clk_div_list[41] = 0b100000001100000000000000000
-clk_div_list[42] = 0b11101011101000110000000000
-clk_div_list[43] = 0b11011001001100100100000000
-clk_div_list[44] = 0b11001001011011101000000000
-clk_div_list[45] = 0b10111011110011010000000000
-clk_div_list[46] = 0b10101111111001100000000000
-clk_div_list[47] = 0b10100101011010100000000000
-clk_div_list[48] = 0b10011100000111000000000000
-clk_div_list[49] = 0b10011100000111000000000000
-clk_div_list[50] = 0b10011100000111000000000000
-clk_div_list[51] = 0b10011100000111000000000000
-clk_div_list[52] = 0b10011100000111000000000000
-clk_div_list[53] = 0b10011100000111000000000000
-clk_div_list[54] = 0b10011100000111000000000000
-clk_div_list[55] = 0b10011100000111000000000000
-clk_div_list[56] = 0b10011100000111000000000000
-clk_div_list[57] = 0b10011100000111000000000000
-clk_div_list[58] = 0b10011100000111000000000000
-clk_div_list[59] = 0b10011100000111000000000000
-clk_div_list[60] = 0b10011100000111000000000000
-clk_div_list[61] = 0b10011100000111000000000000
-clk_div_list[62] = 0b10011100000111000000000000
-clk_div_list[63] = 0b10011100000111000000000000
+clk_div_list[0] = -0b1010110011101010011100100000000
+clk_div_list[1] = -0b1010110011101010011100100000000
+clk_div_list[2] = -0b1010110011101010011100100000000
+clk_div_list[3] = 0b1100101101111110001011100000000
+clk_div_list[4] = 0b1010100110001010110001100000000
+clk_div_list[5] = 0b1010100110001010110001100000000
+clk_div_list[6] = 0b111111100101100010100100000000
+clk_div_list[7] = 0b111000100000111001011100000000
+clk_div_list[8] = 0b110011100101111111001000000000
+clk_div_list[9] = 0b110010110111100011000000000000
+clk_div_list[10] = 0b101110001111100011111000000000
+clk_div_list[11] = 0b101010011000101011000100000000
+clk_div_list[12] = 0b100011010100100011111000000000
+clk_div_list[13] = 0b11110010001100111111000000000
+clk_div_list[14] = 0b11010011111011010111100000000
+clk_div_list[15] = 0b10111111010111101100100000000
+clk_div_list[16] = 0b10111100011000010100100000000
+clk_div_list[17] = 0b10101001100010101100000000000
+clk_div_list[18] = 0b10011010001000010001000000000
+clk_div_list[19] = 0b10001101010010001111100000000
+clk_div_list[20] = 0b10000010011010101100000000000
+clk_div_list[21] = 0b1111001000110011111100000000
+clk_div_list[22] = 0b1110010000110010000000000000
+clk_div_list[23] = 0b1110001000001110010100000000
+clk_div_list[24] = 0b1101001111101101011100000000
+clk_div_list[25] = 0b1100011101110110000100000000
+clk_div_list[26] = 0b1011110001100001010000000000
+clk_div_list[27] = 0b1011001001110111001000000000
+clk_div_list[28] = 0b1010100110001010110000000000
+clk_div_list[29] = 0b1010001010001110101000000000
+clk_div_list[30] = 0b1010000101110111111100000000
+clk_div_list[31] = 0b1001101000100001000100000000
+clk_div_list[32] = 0b1001001101101101100000000000
+clk_div_list[33] = 0b1000110101001000010100000000
+clk_div_list[34] = 0b1000011110100001100100000000
+clk_div_list[35] = 0b1000001001101010001100000000
+clk_div_list[36] = 0b111111000111110000000000000
+clk_div_list[37] = 0b111110110010101101100000000
+clk_div_list[38] = 0b111100100011001100000000000
+clk_div_list[39] = 0b111010011101100100000000000
+clk_div_list[40] = 0b111000100000110110000000000
+clk_div_list[41] = 0b110110101100001011000000000
+clk_div_list[42] = 0b110100111110110010100000000
+clk_div_list[43] = 0b110011100110000111100000000
+clk_div_list[44] = 0b110011011000000010100000000
+clk_div_list[45] = 0b110001110111010101100000000
+clk_div_list[46] = 0b110000011100001010000000000
+clk_div_list[47] = 0b101111000110000010100000000
+clk_div_list[48] = 0b101101110100100101000000000
+clk_div_list[49] = 0b101100100111011010000000000
+clk_div_list[50] = 0b101011101000010001000000000
+clk_div_list[51] = 0b101011011110001100100000000
+clk_div_list[52] = 0b101010011000101001000000000
+clk_div_list[53] = 0b101001010110011110100000000
+clk_div_list[54] = 0b101000010111011110000000000
+clk_div_list[55] = 0b100111011011011001000000000
+clk_div_list[56] = 0b100110100010000010100000000
+clk_div_list[57] = 0b100101110010110011000000000
+clk_div_list[58] = 0b100101101011001111000000000
+clk_div_list[59] = 0b100100110110110100100000000
+clk_div_list[60] = 0b100100000100100111000000000
+clk_div_list[61] = 0b100011010100100001000000000
+clk_div_list[62] = 0b100010100110011000100000000
+clk_div_list[63] = 0b100001111010000110000000000
 
 pwm_freq_list = [
     "0.4 Hz",
@@ -333,4 +333,5 @@
 pwm_div_list[60] = 0b10011100000111000000000000
 pwm_div_list[61] = 0b10011100000111000000000000
 pwm_div_list[62] = 0b10011100000111000000000000
-pwm_div_list[63] = 0b10011100000111000000000000
+pwm_div_list[63] = 0b10011100000111000000000000
+

v10_prototype_version_2/20220109/ecu_simulator_v1.py

@@ -227,6 +227,10 @@ def init_channels():
 mem_slot_1_active = False
 
 def fill_mem_slot(n, z, p1=True, p2=True, p3=True, p4=True):
+    p1 = True
+    p2 = True
+    p3 = True
+    p4 = True
     global d0
     global ar_p
     global mem_slot_1_active
@@ -559,6 +563,7 @@ def signal():
             #todo: register ueberschreiben fuer frequenz
             SM0_CLKDIV = 0x50200000 + 0x0c8
             mem32[SM0_CLKDIV] = clk_div_list[actual_poti[0]//16]
+            #mem32[SM0_CLKDIV] = clk_div_list[3]
             if (actual_poti[0]//16 == 0 and sm_active):
                 sm.active(0)
                 sm_active = False
@@ -628,4 +633,5 @@ def signal():
 
     last_gpio = actual_gpio
 
-    sleep(0.1)
+    sleep(0.1)
+

v10_prototype_version_2/20220109/helper.py

@@ -87,4 +87,5 @@ def suppress(s, p1, p2, p3, p4):
     assert suppress(signal_d, True, False, True, True) == "10000001011001"
     assert suppress(signal_d, True, True, False, True) == "10111000011001"
     assert suppress(signal_d, True, True, True, False) == "10111001000001"
-    assert suppress(signal_d, False, True, False, True) == "00111000011000"
+    assert suppress(signal_d, False, True, False, True) == "00111000011000"
+    

v10_prototype_version_2/20220109/test_02_calc_hash_2.py

@@ -1,6 +1,3 @@
-
-
-
 #freq_list = [5,10,100]
 freq_list = [2.5,2.5,4.166,5,5,6.666,7.5,8.333,9.166,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,66,68,70,72,74,76,78,80,82,84,86,88,90,92,94,96,98,100]
 if len(freq_list)<3:
@@ -31,14 +28,16 @@
         ad = ad+dr
         #print(i, j, freq_list[j], "-", freq_list[min(j+1,len(freq_list)-1)], ad)
         #print(i, j, freq_list[j]+ad)
-        print("*")
+        #print("*")
         freq_list2[i] = freq_list[j]+ad
     else:
         #print(i, j, freq_list[j], "*")
         freq_list2[i] = freq_list[j]
         ad = 0
     k = j
 
+print("hallo")
+print(len(freq_list))
 print(freq_list2)
 
 pwm_list2 = [0]*64
@@ -170,7 +169,7 @@ def signal():
 print()
 for i in range(64):
     #print(clk_freq_list[i])
-    print("clk_div_list["+str(i)+"] = "+pwm_div_list[i])
+    print("clk_div_list["+str(i)+"] = "+clk_div_list[i])
 
 print()
 print("pwm_freq_list = [")
@@ -184,4 +183,5 @@ def signal():
 print()
 for i in range(64):
     #print(clk_freq_list[i])
-    print("pwm_div_list["+str(i)+"] = "+pwm_div_list[i]) 
+    print("pwm_div_list["+str(i)+"] = "+pwm_div_list[i]) 
+