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12 changes: 9 additions & 3 deletions README.md
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Expand Up @@ -17,6 +17,7 @@ Hardware – PCs, Cyclone II , USB flasher
**Theory**

**Logic Diagram**
![DE EXP2 'RTL REALIZATION](https://github.com/naavaneetha/BOOLEAN_FUNCTION_MINIMIZATION/assets/149148235/87af3338-b79a-4298-8558-2e386c410398)

**Procedure**

Expand All @@ -34,18 +35,23 @@ Hardware – PCs, Cyclone II , USB flasher
**Program:**

/* Program to implement the given logic function and to verify its operations in quartus using Verilog programming.
![EXP 2 DE PRG](https://github.com/naavaneetha/BOOLEAN_FUNCTION_MINIMIZATION/assets/149148235/a02c9ea2-ff24-4b07-9945-2c9c072356ea)


Developed by: KAMALESH S
RegisterNumber: 212223040083


Developed by: RegisterNumber:*/


**RTL realization**

**Output:**


**RTL**

**Timing Diagram**

![EXP 2 DE WF](https://github.com/naavaneetha/BOOLEAN_FUNCTION_MINIMIZATION/assets/149148235/06805e8f-7f77-4cb4-af19-fd5b9a3d3f60)
**Result:**

Thus the given logic functions are implemented using and their operations are verified using Verilog programming.
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