From d4ee102a12df5e144e30c08ba9dda8e6f80934e8 Mon Sep 17 00:00:00 2001
From: senthil77k <148571479+senthil77k@users.noreply.github.com>
Date: Mon, 29 Apr 2024 08:23:45 +0530
Subject: [PATCH] Update README.md

---
 README.md | 21 ++++++++++++++++-----
 1 file changed, 16 insertions(+), 5 deletions(-)

diff --git a/README.md b/README.md
index 66006445..cab656a0 100644
--- a/README.md
+++ b/README.md
@@ -32,19 +32,30 @@ Hardware – PCs, Cyclone II , USB flasher
 
 
 **Program:**
+~~~
+module experiment2(E,F,A,B,C,D);
+output E,F;
+input A,B,C,D;
+assign E=A||(B&&C)||((!B)&&D);
+assign F=((!B)&&C)||(B&&(!C)&&(!D));
+endmodule
 
-/* Program to implement the given logic function and to verify its operations in quartus using Verilog programming. 
+~~~
+# Name: senthilkumaran c
+# Register Number:212223220103
 
-Developed by: RegisterNumber:*/
 
+**Truth Table**
 
-**RTL realization**
+![WhatsApp Image 2024-04-04 at 14 56 21_aac75d60](https://github.com/Dharsanrameshkumar/BOOLEAN_FUNCTION_MINIMIZATION/assets/144870430/2b368c66-759e-4aef-9db7-d1b2bf6746bb)
 
-**Output:**
 
 **RTL**
+![WhatsApp Image 2024-04-04 at 14 06 48_dad00aa9](https://github.com/Dharsanrameshkumar/BOOLEAN_FUNCTION_MINIMIZATION/assets/144870430/8fae5a41-dbce-4653-8a93-3ae7fefb7f77)
+
+**Output:**
+![WhatsApp Image 2024-04-04 at 14 07 01_0397bcca](https://github.com/Dharsanrameshkumar/BOOLEAN_FUNCTION_MINIMIZATION/assets/144870430/a3cab865-f1eb-406e-8636-40ca430ddc08)
 
-**Timing Diagram**
 
 **Result:**