32-Bit-Non-Pipelined-Single-Cycle-Processor/Processor_design_nativelink_simulation.rpt at main · namiwijeuom/32-Bit-Non-Pipelined-Single-Cycle-Processor · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Info: Start Nativelink Simulation process
Info: NativeLink has detected Verilog design -- Verilog simulation models will be used

========= EDA Simulation Settings =====================

Sim Mode              :  RTL
Family                :  cycloneive
Quartus root          :  c:/intelfpga_lite/20.1/quartus/bin64/
Quartus sim root      :  c:/intelfpga_lite/20.1/quartus/eda/sim_lib
Simulation Tool       :  modelsim-altera
Simulation Language   :  verilog
Simulation Mode       :  GUI
Sim Output File       :
Sim SDF file          :
Sim dir               :  simulation\modelsim

=======================================================

Info: Starting NativeLink simulation with ModelSim-Altera software
Sourced NativeLink script c:/intelfpga_lite/20.1/quartus/common/tcl/internal/nativelink/modelsim.tcl
Warning: File Processor_design_run_msim_rtl_verilog.do already exists - backing up current file as Processor_design_run_msim_rtl_verilog.do.bak11
Info: Spawning ModelSim-Altera Simulation software
Info: NativeLink simulation flow was successful