The bug caused by the order of `lower` and `ssa`

[weiwenhao]

Following the SSA phase, the temp_var generated in the lower phase was not constructed during the live-in phase of SSA. This resulted in missing virtual register replacements during register allocation.

In fact, the linear scan register paper proposed a coarse-grained live estimation scheme. It was previously discovered that this caused virtual register replacement exceptions due to live omissions. The solution at the time was to replace the coarse-grained live estimation with the precise live estimation from SSA. Now, the real issue might be the omission of lower temporary variables.

[weiwenhao]

Adjusting the order of lower and SSA operations introduces new issues, such as:

ADD t1, rdx -> t1

⬇️ After SSA

ADD t1.s0, rdx -> t1.s1

AMD64 uses tuples for instructions, and in native mode, the first operand and output of ADD default to the same variable. However, after SSA, t1.s0 and t1.s1 are not the same variable. During register allocation, t1.s0 and t1.s1 may not be assigned to the same register.

[weiwenhao]

The incorrectly computed live of lower's temp is completed by the coarse-grained live of the reg stage. Maybe merge ssa_live and reg_live