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vr.map.rpt
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Analysis & Synthesis report for vr
Fri Jun 2 10:39:18 2017
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Analysis & Synthesis RAM Summary
9. Analysis & Synthesis IP Cores Summary
10. State Machine - |vr|playrec:rc|streg
11. State Machine - |vr|Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|s_alavon_slave
12. State Machine - |vr|Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|Altera_UP_I2C:I2C_Controller|s_i2c_transceiver
13. State Machine - |vr|Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|Altera_UP_I2C_AV_Auto_Initialize:Auto_Initialize|s_i2c_auto_init
14. State Machine - |vr|sdram:ram|m_next
15. State Machine - |vr|sdram:ram|m_state
16. State Machine - |vr|sdram:ram|i_next
17. State Machine - |vr|sdram:ram|i_state
18. Registers Removed During Synthesis
19. Removed Registers Triggering Further Register Optimizations
20. General Register Statistics
21. Inverted Register Statistics
22. Multiplexer Restructuring Statistics (Restructuring Performed)
23. Source assignments for sdram:ram
24. Source assignments for Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram
25. Source assignments for Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram
26. Source assignments for Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram
27. Source assignments for Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram
28. Source assignments for vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated
29. Source assignments for vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1
30. Parameter Settings for User Entity Instance: SDRAM_PLL:pll|altpll:altpll_component
31. Parameter Settings for User Entity Instance: Audio_Controller:Audio_Controller
32. Parameter Settings for User Entity Instance: Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer
33. Parameter Settings for User Entity Instance: Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_Audio_Bit_Counter:Audio_Out_Bit_Counter
34. Parameter Settings for User Entity Instance: Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO
35. Parameter Settings for User Entity Instance: Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO
36. Parameter Settings for User Entity Instance: Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Right_Channel_FIFO
37. Parameter Settings for User Entity Instance: Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Right_Channel_FIFO|scfifo:Sync_FIFO
38. Parameter Settings for User Entity Instance: Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer
39. Parameter Settings for User Entity Instance: Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO
40. Parameter Settings for User Entity Instance: Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO
41. Parameter Settings for User Entity Instance: Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO
42. Parameter Settings for User Entity Instance: Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO
43. Parameter Settings for User Entity Instance: Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config
44. Parameter Settings for User Entity Instance: Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|Altera_UP_Slow_Clock_Generator:Clock_Generator_400KHz
45. Parameter Settings for User Entity Instance: Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|Altera_UP_I2C_AV_Auto_Initialize:Auto_Initialize
46. Parameter Settings for User Entity Instance: Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|Altera_UP_I2C:I2C_Controller
47. Parameter Settings for User Entity Instance: vga_adapter:VGA
48. Parameter Settings for User Entity Instance: vga_adapter:VGA|vga_address_translator:user_input_translator
49. Parameter Settings for User Entity Instance: vga_adapter:VGA|altsyncram:VideoMemory
50. Parameter Settings for User Entity Instance: vga_adapter:VGA|vga_controller:controller
51. Parameter Settings for User Entity Instance: vga_adapter:VGA|vga_controller:controller|vga_address_translator:controller_translator
52. Parameter Settings for Inferred Entity Instance: playrec:rc|filter1:filter|lpm_mult:Mult3
53. Parameter Settings for Inferred Entity Instance: playrec:rc|filter3:hc1|lpm_mult:Mult3
54. Parameter Settings for Inferred Entity Instance: playrec:rc|filter3:hc1|lpm_mult:Mult2
55. Parameter Settings for Inferred Entity Instance: playrec:rc|filter4:hc|lpm_mult:Mult3
56. Parameter Settings for Inferred Entity Instance: playrec:rc|filter1:filter|lpm_mult:Mult1
57. Parameter Settings for Inferred Entity Instance: playrec:rc|filter3:hc1|lpm_mult:Mult1
58. Parameter Settings for Inferred Entity Instance: playrec:rc|filter4:hc|lpm_mult:Mult2
59. Parameter Settings for Inferred Entity Instance: playrec:rc|filter1:filter|lpm_mult:Mult0
60. Parameter Settings for Inferred Entity Instance: playrec:rc|filter3:hc1|lpm_mult:Mult0
61. Parameter Settings for Inferred Entity Instance: playrec:rc|filter4:hc|lpm_mult:Mult1
62. Parameter Settings for Inferred Entity Instance: playrec:rc|filter4:hc|lpm_mult:Mult0
63. altpll Parameter Settings by Entity Instance
64. scfifo Parameter Settings by Entity Instance
65. altsyncram Parameter Settings by Entity Instance
66. lpm_mult Parameter Settings by Entity Instance
67. Port Connectivity Checks: "hex2seg:h3"
68. Port Connectivity Checks: "display:disp"
69. Port Connectivity Checks: "Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|Altera_UP_I2C:I2C_Controller"
70. Port Connectivity Checks: "Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|Altera_UP_Slow_Clock_Generator:Clock_Generator_400KHz"
71. Port Connectivity Checks: "Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config"
72. Port Connectivity Checks: "Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer"
73. Port Connectivity Checks: "Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer"
74. Port Connectivity Checks: "Audio_Controller:Audio_Controller"
75. Port Connectivity Checks: "sdram:ram|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module"
76. Port Connectivity Checks: "sdram:ram"
77. Elapsed Time Per Partition
78. Analysis & Synthesis Messages
79. Analysis & Synthesis Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Fri Jun 2 10:39:18 2017 ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; vr ;
; Top-level Entity Name ; vr ;
; Family ; Cyclone II ;
; Total logic elements ; 2,588 ;
; Total combinational functions ; 2,361 ;
; Dedicated logic registers ; 1,239 ;
; Total registers ; 1239 ;
; Total pins ; 159 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 87,040 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 1 ;
+------------------------------------+-------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP2C35F672C6 ; ;
; Top-level entity name ; vr ; vr ;
; Family name ; Cyclone II ; Cyclone IV GX ;
; Use smart compilation ; On ; Off ;
; Maximum processors allowed for parallel compilation ; 4 ; ;
; Verilog Show LMF Mapping Messages ; Off ; ;
; Verilog Version ; SystemVerilog_2005 ; Verilog_2001 ;
; State Machine Processing ; User-Encoded ; Auto ;
; Optimization Technique ; Speed ; Balanced ;
; Allow Any Shift Register Size For Recognition ; On ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; Off ; Off ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; Off ; Off ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
; Synthesis Seed ; 1 ; 1 ;
+----------------------------------------------------------------------------+--------------------+--------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+-----------------------------------------------------+-----------------+-----------------------------------+------------------------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+-----------------------------------------------------+-----------------+-----------------------------------+------------------------------------------------------------------------------------------------+---------+
; audio_controller/Altera_UP_Audio_Bit_Counter.v ; yes ; User Verilog HDL File ; /home/nelson/Downloads/voice_recorder_demo/audio_controller/Altera_UP_Audio_Bit_Counter.v ; ;
; audio_controller/Altera_UP_Audio_In_Deserializer.v ; yes ; User Verilog HDL File ; /home/nelson/Downloads/voice_recorder_demo/audio_controller/Altera_UP_Audio_In_Deserializer.v ; ;
; audio_controller/Altera_UP_Audio_Out_Serializer.v ; yes ; User Verilog HDL File ; /home/nelson/Downloads/voice_recorder_demo/audio_controller/Altera_UP_Audio_Out_Serializer.v ; ;
; audio_controller/Altera_UP_Clock_Edge.v ; yes ; User Verilog HDL File ; /home/nelson/Downloads/voice_recorder_demo/audio_controller/Altera_UP_Clock_Edge.v ; ;
; audio_controller/Altera_UP_I2C.v ; yes ; User Verilog HDL File ; /home/nelson/Downloads/voice_recorder_demo/audio_controller/Altera_UP_I2C.v ; ;
; audio_controller/Altera_UP_I2C_AV_Auto_Initialize.v ; yes ; User Verilog HDL File ; /home/nelson/Downloads/voice_recorder_demo/audio_controller/Altera_UP_I2C_AV_Auto_Initialize.v ; ;
; audio_controller/Altera_UP_Slow_Clock_Generator.v ; yes ; User Verilog HDL File ; /home/nelson/Downloads/voice_recorder_demo/audio_controller/Altera_UP_Slow_Clock_Generator.v ; ;
; audio_controller/Altera_UP_SYNC_FIFO.v ; yes ; User Verilog HDL File ; /home/nelson/Downloads/voice_recorder_demo/audio_controller/Altera_UP_SYNC_FIFO.v ; ;
; audio_controller/Audio_and_Video_Config.v ; yes ; User Verilog HDL File ; /home/nelson/Downloads/voice_recorder_demo/audio_controller/Audio_and_Video_Config.v ; ;
; audio_controller/Audio_Controller.v ; yes ; User Verilog HDL File ; /home/nelson/Downloads/voice_recorder_demo/audio_controller/Audio_Controller.v ; ;
; vga_adapter/vga_adapter.v ; yes ; User Verilog HDL File ; /home/nelson/Downloads/voice_recorder_demo/vga_adapter/vga_adapter.v ; ;
; vga_adapter/vga_address_translator.v ; yes ; User Verilog HDL File ; /home/nelson/Downloads/voice_recorder_demo/vga_adapter/vga_address_translator.v ; ;
; vga_adapter/vga_controller.v ; yes ; User Verilog HDL File ; /home/nelson/Downloads/voice_recorder_demo/vga_adapter/vga_controller.v ; ;
; sdram.v ; yes ; User Verilog HDL File ; /home/nelson/Downloads/voice_recorder_demo/sdram.v ; ;
; hex2seg.v ; yes ; User Verilog HDL File ; /home/nelson/Downloads/voice_recorder_demo/hex2seg.v ; ;
; playrec.v ; yes ; User Verilog HDL File ; /home/nelson/Downloads/voice_recorder_demo/playrec.v ; ;
; vr.v ; yes ; User Verilog HDL File ; /home/nelson/Downloads/voice_recorder_demo/vr.v ; ;
; display.v ; yes ; User Verilog HDL File ; /home/nelson/Downloads/voice_recorder_demo/display.v ; ;
; SDRAM_PLL.v ; yes ; Auto-Found Wizard-Generated File ; /home/nelson/Downloads/voice_recorder_demo/SDRAM_PLL.v ; ;
; altpll.tdf ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/altpll.tdf ; ;
; aglobal130.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/aglobal130.inc ; ;
; stratix_pll.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/stratix_pll.inc ; ;
; stratixii_pll.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/stratixii_pll.inc ; ;
; cycloneii_pll.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/cycloneii_pll.inc ; ;
; scfifo.tdf ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/scfifo.tdf ; ;
; a_regfifo.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/a_regfifo.inc ; ;
; a_dpfifo.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/a_dpfifo.inc ; ;
; a_i2fifo.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/a_i2fifo.inc ; ;
; a_fffifo.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/a_fffifo.inc ; ;
; a_f2fifo.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/a_f2fifo.inc ; ;
; db/scfifo_5041.tdf ; yes ; Auto-Generated Megafunction ; /home/nelson/Downloads/voice_recorder_demo/db/scfifo_5041.tdf ; ;
; db/a_dpfifo_on31.tdf ; yes ; Auto-Generated Megafunction ; /home/nelson/Downloads/voice_recorder_demo/db/a_dpfifo_on31.tdf ; ;
; db/altsyncram_rc81.tdf ; yes ; Auto-Generated Megafunction ; /home/nelson/Downloads/voice_recorder_demo/db/altsyncram_rc81.tdf ; ;
; db/cmpr_2o8.tdf ; yes ; Auto-Generated Megafunction ; /home/nelson/Downloads/voice_recorder_demo/db/cmpr_2o8.tdf ; ;
; db/cntr_d5b.tdf ; yes ; Auto-Generated Megafunction ; /home/nelson/Downloads/voice_recorder_demo/db/cntr_d5b.tdf ; ;
; db/cntr_q57.tdf ; yes ; Auto-Generated Megafunction ; /home/nelson/Downloads/voice_recorder_demo/db/cntr_q57.tdf ; ;
; db/cntr_e5b.tdf ; yes ; Auto-Generated Megafunction ; /home/nelson/Downloads/voice_recorder_demo/db/cntr_e5b.tdf ; ;
; altsyncram.tdf ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf ; ;
; stratix_ram_block.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/stratix_ram_block.inc ; ;
; lpm_mux.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mux.inc ; ;
; lpm_decode.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/lpm_decode.inc ; ;
; a_rdenreg.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/a_rdenreg.inc ; ;
; altrom.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/altrom.inc ; ;
; altram.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/altram.inc ; ;
; altdpram.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/altdpram.inc ; ;
; db/altsyncram_9dg1.tdf ; yes ; Auto-Generated Megafunction ; /home/nelson/Downloads/voice_recorder_demo/db/altsyncram_9dg1.tdf ; ;
; db/altsyncram_97r1.tdf ; yes ; Auto-Generated Megafunction ; /home/nelson/Downloads/voice_recorder_demo/db/altsyncram_97r1.tdf ; ;
; db/decode_tpa.tdf ; yes ; Auto-Generated Megafunction ; /home/nelson/Downloads/voice_recorder_demo/db/decode_tpa.tdf ; ;
; db/mux_6kb.tdf ; yes ; Auto-Generated Megafunction ; /home/nelson/Downloads/voice_recorder_demo/db/mux_6kb.tdf ; ;
; lpm_mult.tdf ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf ; ;
; lpm_add_sub.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.inc ; ;
; multcore.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/multcore.inc ; ;
; bypassff.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/bypassff.inc ; ;
; altshift.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/altshift.inc ; ;
; multcore.tdf ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf ; ;
; csa_add.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/csa_add.inc ; ;
; mpar_add.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/mpar_add.inc ; ;
; muleabz.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/muleabz.inc ; ;
; mul_lfrg.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/mul_lfrg.inc ; ;
; mul_boothc.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/mul_boothc.inc ; ;
; alt_ded_mult.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/alt_ded_mult.inc ; ;
; alt_ded_mult_y.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/alt_ded_mult_y.inc ; ;
; dffpipe.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/dffpipe.inc ; ;
; mpar_add.tdf ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/mpar_add.tdf ; ;
; lpm_add_sub.tdf ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf ; ;
; addcore.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/addcore.inc ; ;
; look_add.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/look_add.inc ; ;
; alt_stratix_add_sub.inc ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ; ;
; db/add_sub_deh.tdf ; yes ; Auto-Generated Megafunction ; /home/nelson/Downloads/voice_recorder_demo/db/add_sub_deh.tdf ; ;
; db/add_sub_j3h.tdf ; yes ; Auto-Generated Megafunction ; /home/nelson/Downloads/voice_recorder_demo/db/add_sub_j3h.tdf ; ;
; db/add_sub_ofh.tdf ; yes ; Auto-Generated Megafunction ; /home/nelson/Downloads/voice_recorder_demo/db/add_sub_ofh.tdf ; ;
; altshift.tdf ; yes ; Megafunction ; /home/nelson/altera/13.0sp1/quartus/libraries/megafunctions/altshift.tdf ; ;
; db/add_sub_55h.tdf ; yes ; Auto-Generated Megafunction ; /home/nelson/Downloads/voice_recorder_demo/db/add_sub_55h.tdf ; ;
; db/add_sub_feh.tdf ; yes ; Auto-Generated Megafunction ; /home/nelson/Downloads/voice_recorder_demo/db/add_sub_feh.tdf ; ;
; db/add_sub_l3h.tdf ; yes ; Auto-Generated Megafunction ; /home/nelson/Downloads/voice_recorder_demo/db/add_sub_l3h.tdf ; ;
; db/add_sub_qfh.tdf ; yes ; Auto-Generated Megafunction ; /home/nelson/Downloads/voice_recorder_demo/db/add_sub_qfh.tdf ; ;
; db/add_sub_eeh.tdf ; yes ; Auto-Generated Megafunction ; /home/nelson/Downloads/voice_recorder_demo/db/add_sub_eeh.tdf ; ;
; db/add_sub_k3h.tdf ; yes ; Auto-Generated Megafunction ; /home/nelson/Downloads/voice_recorder_demo/db/add_sub_k3h.tdf ; ;
; db/add_sub_tfh.tdf ; yes ; Auto-Generated Megafunction ; /home/nelson/Downloads/voice_recorder_demo/db/add_sub_tfh.tdf ; ;
; db/add_sub_v4h.tdf ; yes ; Auto-Generated Megafunction ; /home/nelson/Downloads/voice_recorder_demo/db/add_sub_v4h.tdf ; ;
; db/add_sub_vfh.tdf ; yes ; Auto-Generated Megafunction ; /home/nelson/Downloads/voice_recorder_demo/db/add_sub_vfh.tdf ; ;
; db/add_sub_u4h.tdf ; yes ; Auto-Generated Megafunction ; /home/nelson/Downloads/voice_recorder_demo/db/add_sub_u4h.tdf ; ;
; db/add_sub_sfh.tdf ; yes ; Auto-Generated Megafunction ; /home/nelson/Downloads/voice_recorder_demo/db/add_sub_sfh.tdf ; ;
; db/add_sub_05h.tdf ; yes ; Auto-Generated Megafunction ; /home/nelson/Downloads/voice_recorder_demo/db/add_sub_05h.tdf ; ;
; db/add_sub_ufh.tdf ; yes ; Auto-Generated Megafunction ; /home/nelson/Downloads/voice_recorder_demo/db/add_sub_ufh.tdf ; ;
+-----------------------------------------------------+-----------------+-----------------------------------+------------------------------------------------------------------------------------------------+---------+
+--------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+----------+
; Resource ; Usage ;
+---------------------------------------------+----------+
; Estimated Total logic elements ; 2,588 ;
; ; ;
; Total combinational functions ; 2361 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 901 ;
; -- 3 input functions ; 978 ;
; -- <=2 input functions ; 482 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 1362 ;
; -- arithmetic mode ; 999 ;
; ; ;
; Total registers ; 1239 ;
; -- Dedicated logic registers ; 1239 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 159 ;
; Total memory bits ; 87040 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 1 ;
; -- PLLs ; 1 ;
; ; ;
; Maximum fan-out node ; CLOCK_50 ;
; Maximum fan-out ; 1303 ;
; Total fan-out ; 12884 ;
; Average fan-out ; 3.34 ;
+---------------------------------------------+----------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+-------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |vr ; 2361 (123) ; 1239 (26) ; 87040 ; 0 ; 0 ; 0 ; 159 ; 0 ; |vr ; work ;
; |Audio_Controller:Audio_Controller| ; 513 (4) ; 257 (4) ; 10240 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller ; work ;
; |Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer| ; 124 (41) ; 87 (36) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer ; work ;
; |Altera_UP_Audio_Bit_Counter:Audio_Out_Bit_Counter| ; 10 (10) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_Audio_Bit_Counter:Audio_Out_Bit_Counter ; work ;
; |Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO| ; 52 (0) ; 33 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO ; work ;
; |scfifo:Sync_FIFO| ; 52 (0) ; 33 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO ; work ;
; |scfifo_5041:auto_generated| ; 52 (0) ; 33 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated ; work ;
; |a_dpfifo_on31:dpfifo| ; 52 (29) ; 33 (13) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo ; work ;
; |altsyncram_rc81:FIFOram| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram ; work ;
; |cntr_d5b:rd_ptr_msb| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|cntr_d5b:rd_ptr_msb ; work ;
; |cntr_e5b:wr_ptr| ; 8 (8) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|cntr_e5b:wr_ptr ; work ;
; |cntr_q57:usedw_counter| ; 8 (8) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|cntr_q57:usedw_counter ; work ;
; |Altera_UP_SYNC_FIFO:Audio_In_Right_Channel_FIFO| ; 21 (0) ; 12 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Right_Channel_FIFO ; work ;
; |scfifo:Sync_FIFO| ; 21 (0) ; 12 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Right_Channel_FIFO|scfifo:Sync_FIFO ; work ;
; |scfifo_5041:auto_generated| ; 21 (0) ; 12 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated ; work ;
; |a_dpfifo_on31:dpfifo| ; 21 (13) ; 12 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo ; work ;
; |cntr_q57:usedw_counter| ; 8 (8) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|cntr_q57:usedw_counter ; work ;
; |Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer| ; 190 (86) ; 104 (38) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer ; work ;
; |Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO| ; 52 (0) ; 33 (0) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO ; work ;
; |scfifo:Sync_FIFO| ; 52 (0) ; 33 (0) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO ; work ;
; |scfifo_5041:auto_generated| ; 52 (0) ; 33 (0) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated ; work ;
; |a_dpfifo_on31:dpfifo| ; 52 (29) ; 33 (13) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo ; work ;
; |altsyncram_rc81:FIFOram| ; 0 (0) ; 0 (0) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram ; work ;
; |cntr_d5b:rd_ptr_msb| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|cntr_d5b:rd_ptr_msb ; work ;
; |cntr_e5b:wr_ptr| ; 8 (8) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|cntr_e5b:wr_ptr ; work ;
; |cntr_q57:usedw_counter| ; 8 (8) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|cntr_q57:usedw_counter ; work ;
; |Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO| ; 52 (0) ; 33 (0) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO ; work ;
; |scfifo:Sync_FIFO| ; 52 (0) ; 33 (0) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO ; work ;
; |scfifo_5041:auto_generated| ; 52 (0) ; 33 (0) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated ; work ;
; |a_dpfifo_on31:dpfifo| ; 52 (29) ; 33 (13) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo ; work ;
; |altsyncram_rc81:FIFOram| ; 0 (0) ; 0 (0) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram ; work ;
; |cntr_d5b:rd_ptr_msb| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|cntr_d5b:rd_ptr_msb ; work ;
; |cntr_e5b:wr_ptr| ; 8 (8) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|cntr_e5b:wr_ptr ; work ;
; |cntr_q57:usedw_counter| ; 8 (8) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|cntr_q57:usedw_counter ; work ;
; |Altera_UP_Clock_Edge:ADC_Left_Right_Clock_Edges| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Clock_Edge:ADC_Left_Right_Clock_Edges ; work ;
; |Altera_UP_Clock_Edge:Bit_Clock_Edges| ; 1 (1) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Clock_Edge:Bit_Clock_Edges ; work ;
; |Altera_UP_Clock_Edge:DAC_Left_Right_Clock_Edges| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Clock_Edge:DAC_Left_Right_Clock_Edges ; work ;
; |Audio_and_Video_Config:Audio_Config| ; 194 (10) ; 56 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config ; work ;
; |Altera_UP_I2C:I2C_Controller| ; 43 (43) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|Altera_UP_I2C:I2C_Controller ; work ;
; |Altera_UP_I2C_AV_Auto_Initialize:Auto_Initialize| ; 125 (125) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|Altera_UP_I2C_AV_Auto_Initialize:Auto_Initialize ; work ;
; |Altera_UP_Slow_Clock_Generator:Clock_Generator_400KHz| ; 16 (16) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|Altera_UP_Slow_Clock_Generator:Clock_Generator_400KHz ; work ;
; |SDRAM_PLL:pll| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|SDRAM_PLL:pll ; work ;
; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|SDRAM_PLL:pll|altpll:altpll_component ; work ;
; |display:disp| ; 82 (82) ; 50 (50) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|display:disp ; work ;
; |hex2seg:h0| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|hex2seg:h0 ; work ;
; |hex2seg:h1| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|hex2seg:h1 ; work ;
; |hex2seg:h3| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|hex2seg:h3 ; work ;
; |hex2seg:h4| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|hex2seg:h4 ; work ;
; |playrec:rc| ; 1042 (122) ; 645 (25) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc ; work ;
; |filter1:filter| ; 307 (156) ; 168 (168) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter ; work ;
; |lpm_mult:Mult0| ; 49 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult0 ; work ;
; |multcore:mult_core| ; 49 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult0|multcore:mult_core ; work ;
; |mpar_add:padder| ; 40 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder ; work ;
; |lpm_add_sub:adder[0]| ; 12 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0] ; work ;
; |add_sub_05h:auto_generated| ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_05h:auto_generated ; work ;
; |lpm_add_sub:adder[1]| ; 12 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1] ; work ;
; |add_sub_qfh:auto_generated| ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|add_sub_qfh:auto_generated ; work ;
; |mpar_add:sub_par_add| ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add ; work ;
; |lpm_add_sub:adder[0]| ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0] ; work ;
; |add_sub_ufh:auto_generated| ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_ufh:auto_generated ; work ;
; |lpm_mult:Mult1| ; 61 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult1 ; work ;
; |multcore:mult_core| ; 61 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult1|multcore:mult_core ; work ;
; |mpar_add:padder| ; 37 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder ; work ;
; |lpm_add_sub:adder[0]| ; 11 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0] ; work ;
; |add_sub_v4h:auto_generated| ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_v4h:auto_generated ; work ;
; |lpm_add_sub:adder[1]| ; 11 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1] ; work ;
; |add_sub_tfh:auto_generated| ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|add_sub_tfh:auto_generated ; work ;
; |mpar_add:sub_par_add| ; 15 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add ; work ;
; |lpm_add_sub:adder[0]| ; 15 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0] ; work ;
; |add_sub_vfh:auto_generated| ; 15 (15) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_vfh:auto_generated ; work ;
; |lpm_mult:Mult3| ; 41 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult3 ; work ;
; |multcore:mult_core| ; 41 (22) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult3|multcore:mult_core ; work ;
; |mpar_add:padder| ; 19 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult3|multcore:mult_core|mpar_add:padder ; work ;
; |lpm_add_sub:adder[0]| ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0] ; work ;
; |add_sub_j3h:auto_generated| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_j3h:auto_generated ; work ;
; |lpm_add_sub:adder[1]| ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1] ; work ;
; |add_sub_deh:auto_generated| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|add_sub_deh:auto_generated ; work ;
; |mpar_add:sub_par_add| ; 9 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult3|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add ; work ;
; |lpm_add_sub:adder[0]| ; 9 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult3|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0] ; work ;
; |add_sub_ofh:auto_generated| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter1:filter|lpm_mult:Mult3|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_ofh:auto_generated ; work ;
; |filter2:echo| ; 16 (16) ; 121 (121) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter2:echo ; work ;
; |filter3:hc1| ; 344 (163) ; 173 (173) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1 ; work ;
; |lpm_mult:Mult0| ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult0 ; work ;
; |multcore:mult_core| ; 60 (23) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult0|multcore:mult_core ; work ;
; |mpar_add:padder| ; 37 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder ; work ;
; |lpm_add_sub:adder[0]| ; 11 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0] ; work ;
; |add_sub_05h:auto_generated| ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_05h:auto_generated ; work ;
; |lpm_add_sub:adder[1]| ; 11 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1] ; work ;
; |add_sub_qfh:auto_generated| ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|add_sub_qfh:auto_generated ; work ;
; |mpar_add:sub_par_add| ; 15 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add ; work ;
; |lpm_add_sub:adder[0]| ; 15 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0] ; work ;
; |add_sub_ufh:auto_generated| ; 15 (15) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_ufh:auto_generated ; work ;
; |lpm_mult:Mult1| ; 61 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult1 ; work ;
; |multcore:mult_core| ; 61 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult1|multcore:mult_core ; work ;
; |mpar_add:padder| ; 37 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder ; work ;
; |lpm_add_sub:adder[0]| ; 11 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0] ; work ;
; |add_sub_v4h:auto_generated| ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_v4h:auto_generated ; work ;
; |lpm_add_sub:adder[1]| ; 11 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1] ; work ;
; |add_sub_tfh:auto_generated| ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|add_sub_tfh:auto_generated ; work ;
; |mpar_add:sub_par_add| ; 15 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add ; work ;
; |lpm_add_sub:adder[0]| ; 15 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0] ; work ;
; |add_sub_vfh:auto_generated| ; 15 (15) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_vfh:auto_generated ; work ;
; |lpm_mult:Mult2| ; 44 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult2 ; work ;
; |multcore:mult_core| ; 44 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult2|multcore:mult_core ; work ;
; |mpar_add:padder| ; 28 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder ; work ;
; |lpm_add_sub:adder[0]| ; 8 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0] ; work ;
; |add_sub_l3h:auto_generated| ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_l3h:auto_generated ; work ;
; |lpm_add_sub:adder[1]| ; 8 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1] ; work ;
; |add_sub_feh:auto_generated| ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|add_sub_feh:auto_generated ; work ;
; |mpar_add:sub_par_add| ; 12 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add ; work ;
; |lpm_add_sub:adder[0]| ; 12 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0] ; work ;
; |add_sub_qfh:auto_generated| ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_qfh:auto_generated ; work ;
; |lpm_mult:Mult3| ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult3 ; work ;
; |multcore:mult_core| ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult3|multcore:mult_core ; work ;
; |lpm_add_sub:adder| ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult3|multcore:mult_core|lpm_add_sub:adder ; work ;
; |add_sub_55h:auto_generated| ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter3:hc1|lpm_mult:Mult3|multcore:mult_core|lpm_add_sub:adder|add_sub_55h:auto_generated ; work ;
; |filter4:hc| ; 253 (130) ; 158 (158) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc ; work ;
; |lpm_mult:Mult0| ; 19 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult0 ; work ;
; |multcore:mult_core| ; 19 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult0|multcore:mult_core ; work ;
; |mpar_add:padder| ; 19 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder ; work ;
; |lpm_add_sub:adder[0]| ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0] ; work ;
; |add_sub_v4h:auto_generated| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_v4h:auto_generated ; work ;
; |lpm_add_sub:adder[1]| ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1] ; work ;
; |add_sub_tfh:auto_generated| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|add_sub_tfh:auto_generated ; work ;
; |mpar_add:sub_par_add| ; 9 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add ; work ;
; |lpm_add_sub:adder[0]| ; 9 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0] ; work ;
; |add_sub_vfh:auto_generated| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_vfh:auto_generated ; work ;
; |lpm_mult:Mult1| ; 40 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult1 ; work ;
; |multcore:mult_core| ; 40 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult1|multcore:mult_core ; work ;
; |mpar_add:padder| ; 34 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder ; work ;
; |lpm_add_sub:adder[0]| ; 10 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0] ; work ;
; |add_sub_v4h:auto_generated| ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_v4h:auto_generated ; work ;
; |lpm_add_sub:adder[1]| ; 10 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1] ; work ;
; |add_sub_tfh:auto_generated| ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|add_sub_tfh:auto_generated ; work ;
; |mpar_add:sub_par_add| ; 14 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add ; work ;
; |lpm_add_sub:adder[0]| ; 14 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0] ; work ;
; |add_sub_vfh:auto_generated| ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_vfh:auto_generated ; work ;
; |lpm_mult:Mult2| ; 45 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult2 ; work ;
; |multcore:mult_core| ; 45 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult2|multcore:mult_core ; work ;
; |mpar_add:padder| ; 31 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder ; work ;
; |lpm_add_sub:adder[0]| ; 9 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0] ; work ;
; |add_sub_u4h:auto_generated| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_u4h:auto_generated ; work ;
; |lpm_add_sub:adder[1]| ; 9 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1] ; work ;
; |add_sub_ofh:auto_generated| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|add_sub_ofh:auto_generated ; work ;
; |mpar_add:sub_par_add| ; 13 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add ; work ;
; |lpm_add_sub:adder[0]| ; 13 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0] ; work ;
; |add_sub_sfh:auto_generated| ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_sfh:auto_generated ; work ;
; |lpm_mult:Mult3| ; 19 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult3 ; work ;
; |multcore:mult_core| ; 19 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult3|multcore:mult_core ; work ;
; |mpar_add:padder| ; 19 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult3|multcore:mult_core|mpar_add:padder ; work ;
; |lpm_add_sub:adder[0]| ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0] ; work ;
; |add_sub_k3h:auto_generated| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_k3h:auto_generated ; work ;
; |lpm_add_sub:adder[1]| ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1] ; work ;
; |add_sub_eeh:auto_generated| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|add_sub_eeh:auto_generated ; work ;
; |mpar_add:sub_par_add| ; 9 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult3|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add ; work ;
; |lpm_add_sub:adder[0]| ; 9 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult3|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0] ; work ;
; |add_sub_tfh:auto_generated| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|playrec:rc|filter4:hc|lpm_mult:Mult3|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_tfh:auto_generated ; work ;
; |sdram:ram| ; 401 (354) ; 225 (143) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|sdram:ram ; work ;
; |sdram_0_input_efifo_module:the_sdram_0_input_efifo_module| ; 47 (47) ; 82 (82) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|sdram:ram|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module ; work ;
; |vga_adapter:VGA| ; 176 (2) ; 36 (0) ; 76800 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|vga_adapter:VGA ; work ;
; |altsyncram:VideoMemory| ; 86 (0) ; 10 (0) ; 76800 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|vga_adapter:VGA|altsyncram:VideoMemory ; work ;
; |altsyncram_9dg1:auto_generated| ; 86 (0) ; 10 (0) ; 76800 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated ; work ;
; |altsyncram_97r1:altsyncram1| ; 86 (0) ; 10 (10) ; 76800 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1 ; work ;
; |decode_tpa:decode4| ; 29 (29) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|decode_tpa:decode4 ; work ;
; |decode_tpa:decode_a| ; 24 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|decode_tpa:decode_a ; work ;
; |decode_tpa:decode_b| ; 17 (17) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|decode_tpa:decode_b ; work ;
; |mux_6kb:mux5| ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|mux_6kb:mux5 ; work ;
; |vga_address_translator:user_input_translator| ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|vga_adapter:VGA|vga_address_translator:user_input_translator ; work ;
; |vga_controller:controller| ; 68 (48) ; 26 (26) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|vga_adapter:VGA|vga_controller:controller ; work ;
; |vga_address_translator:controller_translator| ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vr|vga_adapter:VGA|vga_controller:controller|vga_address_translator:controller_translator ; work ;
+-------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 128 ; 32 ; 128 ; 32 ; 4096 ; None ;
; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 128 ; 32 ; 128 ; 32 ; 4096 ; None ;
; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 128 ; 32 ; 128 ; 32 ; 4096 ; None ;
; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ALTSYNCRAM ; AUTO ; True Dual Port ; 76800 ; 1 ; 76800 ; 1 ; 76800 ; None ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
+--------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary ;
+--------+--------------+---------+--------------+--------------+-------------------+--------------------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
+--------+--------------+---------+--------------+--------------+-------------------+--------------------------------------------------------+
; Altera ; ALTPLL ; N/A ; N/A ; N/A ; |vr|SDRAM_PLL:pll ; /home/nelson/Downloads/voice_recorder_demo/SDRAM_PLL.v ;
+--------+--------------+---------+--------------+--------------+-------------------+--------------------------------------------------------+
Encoding Type: User-Encoded
+--------------------------------------------------------+
; State Machine - |vr|playrec:rc|streg ;
+--------------------------+---------+---------+---------+
; Name ; streg~4 ; streg~3 ; streg~2 ;
+--------------------------+---------+---------+---------+
; streg.st_input_check ; 0 ; 0 ; 0 ;
; streg.st_rc_audio_wait ; 1 ; 1 ; 0 ;
; streg.st_rc_ram_nextaddr ; 1 ; 0 ; 1 ;
; streg.st_rc_ram_wait ; 1 ; 0 ; 0 ;
; streg.st_pl_ram_rd ; 0 ; 1 ; 1 ;
; streg.st_pl_audio_wait ; 0 ; 1 ; 0 ;
; streg.st_pl_ram_nextaddr ; 0 ; 0 ; 1 ;
; streg.st_start ; 1 ; 1 ; 1 ;
+--------------------------+---------+---------+---------+
Encoding Type: User-Encoded
+----------------------------------------------------------------------------------------------------------+
; State Machine - |vr|Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|s_alavon_slave ;
+----------------------------------------+------------------+----------------------------------------------+
; Name ; s_alavon_slave~3 ; s_alavon_slave~2 ;
+----------------------------------------+------------------+----------------------------------------------+
; s_alavon_slave.I2C_STATE_0_IDLE ; 0 ; 0 ;
; s_alavon_slave.I2C_STATE_1_START ; 0 ; 1 ;
; s_alavon_slave.I2C_STATE_2_TRANSFERING ; 1 ; 0 ;
; s_alavon_slave.I2C_STATE_3_COMPLETE ; 1 ; 1 ;
+----------------------------------------+------------------+----------------------------------------------+
Encoding Type: User-Encoded
+------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |vr|Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|Altera_UP_I2C:I2C_Controller|s_i2c_transceiver ;
+---------------------------------------------+---------------------+---------------------+------------------------------------------------+
; Name ; s_i2c_transceiver~4 ; s_i2c_transceiver~3 ; s_i2c_transceiver~2 ;
+---------------------------------------------+---------------------+---------------------+------------------------------------------------+
; s_i2c_transceiver.I2C_STATE_0_IDLE ; 0 ; 0 ; 0 ;
; s_i2c_transceiver.I2C_STATE_1_PRE_START ; 0 ; 0 ; 1 ;
; s_i2c_transceiver.I2C_STATE_2_START_BIT ; 0 ; 1 ; 0 ;
; s_i2c_transceiver.I2C_STATE_3_TRANSFER_BYTE ; 0 ; 1 ; 1 ;
; s_i2c_transceiver.I2C_STATE_4_TRANSFER_ACK ; 1 ; 0 ; 0 ;
; s_i2c_transceiver.I2C_STATE_5_STOP_BIT ; 1 ; 0 ; 1 ;
; s_i2c_transceiver.I2C_STATE_6_COMPLETE ; 1 ; 1 ; 0 ;
+---------------------------------------------+---------------------+---------------------+------------------------------------------------+
Encoding Type: User-Encoded
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |vr|Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|Altera_UP_I2C_AV_Auto_Initialize:Auto_Initialize|s_i2c_auto_init ;
+-----------------------------------------------+-------------------+-------------------+--------------------------------------------------------------------+
; Name ; s_i2c_auto_init~4 ; s_i2c_auto_init~3 ; s_i2c_auto_init~2 ;
+-----------------------------------------------+-------------------+-------------------+--------------------------------------------------------------------+
; s_i2c_auto_init.AUTO_STATE_0_CHECK_STATUS ; 0 ; 0 ; 0 ;
; s_i2c_auto_init.AUTO_STATE_1_SEND_START_BIT ; 0 ; 0 ; 1 ;
; s_i2c_auto_init.AUTO_STATE_2_TRANSFER_BYTE_1 ; 0 ; 1 ; 0 ;
; s_i2c_auto_init.AUTO_STATE_3_TRANSFER_BYTE_2 ; 0 ; 1 ; 1 ;
; s_i2c_auto_init.AUTO_STATE_4_WAIT ; 1 ; 0 ; 0 ;
; s_i2c_auto_init.AUTO_STATE_5_SEND_STOP_BIT ; 1 ; 0 ; 1 ;
; s_i2c_auto_init.AUTO_STATE_6_INCREASE_COUNTER ; 1 ; 1 ; 0 ;
; s_i2c_auto_init.AUTO_STATE_7_DONE ; 1 ; 1 ; 1 ;
+-----------------------------------------------+-------------------+-------------------+--------------------------------------------------------------------+
Encoding Type: User-Encoded
+-----------------------------------------------------------------+
; State Machine - |vr|sdram:ram|m_next ;
+------------------+-----------+-----------+-----------+----------+
; Name ; m_next~15 ; m_next~12 ; m_next~11 ; m_next~8 ;
+------------------+-----------+-----------+-----------+----------+
; m_next.000000001 ; 0 ; 0 ; 0 ; 0 ;
; m_next.000001000 ; 0 ; 0 ; 1 ; 1 ;
; m_next.000010000 ; 0 ; 1 ; 0 ; 1 ;
; m_next.010000000 ; 1 ; 0 ; 0 ; 1 ;
+------------------+-----------+-----------+-----------+----------+
Encoding Type: User-Encoded
+----------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |vr|sdram:ram|m_state ;
+-------------------+------------+------------+------------+------------+------------+------------+------------+------------+------------+
; Name ; m_state~21 ; m_state~20 ; m_state~19 ; m_state~18 ; m_state~17 ; m_state~16 ; m_state~15 ; m_state~14 ; m_state~13 ;
+-------------------+------------+------------+------------+------------+------------+------------+------------+------------+------------+
; m_state.000000001 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; m_state.000000010 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;
; m_state.000000100 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
; m_state.000001000 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;
; m_state.000010000 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;
; m_state.000100000 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; m_state.001000000 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; m_state.010000000 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; m_state.100000000 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
+-------------------+------------+------------+------------+------------+------------+------------+------------+------------+------------+
Encoding Type: User-Encoded
+--------------------------------------+
; State Machine - |vr|sdram:ram|i_next ;
+------------+----------+--------------+
; Name ; i_next~5 ; i_next~4 ;
+------------+----------+--------------+
; i_next.000 ; 0 ; 0 ;
; i_next.010 ; 1 ; 0 ;
; i_next.101 ; 0 ; 1 ;
; i_next.111 ; 1 ; 1 ;
+------------+----------+--------------+
Encoding Type: User-Encoded
+----------------------------------------------------+
; State Machine - |vr|sdram:ram|i_state ;
+-------------+------------+------------+------------+
; Name ; i_state~16 ; i_state~15 ; i_state~14 ;
+-------------+------------+------------+------------+
; i_state.000 ; 0 ; 0 ; 0 ;
; i_state.001 ; 0 ; 0 ; 1 ;
; i_state.010 ; 0 ; 1 ; 0 ;
; i_state.011 ; 0 ; 1 ; 1 ;
; i_state.101 ; 1 ; 0 ; 1 ;
; i_state.111 ; 1 ; 1 ; 1 ;
+-------------+------------+------------+------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+
; Register name ; Reason for Removal ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+
; sdram:ram|i_addr[4,5] ; Stuck at VCC due to stuck port data_in ;
; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[0..6] ; Lost fanout ;
; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|rd_ptr_lsb ; Lost fanout ;
; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|cntr_e5b:wr_ptr|safe_q[0..6] ; Lost fanout ;
; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|cntr_d5b:rd_ptr_msb|safe_q[0..5] ; Lost fanout ;
; sdram:ram|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[16,17] ; Stuck at GND due to stuck port data_in ;
; sdram:ram|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[16,17] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter2:echo|y[0][16] ; Merged with playrec:rc|filter2:echo|y[0][15] ;
; Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|num_bits_to_transfer[1,2] ; Merged with Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|num_bits_to_transfer[0] ;
; sdram:ram|i_addr[0..3,6..10] ; Merged with sdram:ram|i_addr[11] ;
; playrec:rc|filter2:echo|y[1][16] ; Merged with playrec:rc|filter2:echo|y[1][15] ;
; playrec:rc|filter2:echo|y[2][16] ; Merged with playrec:rc|filter2:echo|y[2][15] ;
; playrec:rc|filter2:echo|y[3][16] ; Merged with playrec:rc|filter2:echo|y[3][15] ;
; playrec:rc|filter2:echo|y[4][16] ; Merged with playrec:rc|filter2:echo|y[4][15] ;
; playrec:rc|filter2:echo|y[5][16] ; Merged with playrec:rc|filter2:echo|y[5][15] ;
; playrec:rc|filter2:echo|y[6][16] ; Merged with playrec:rc|filter2:echo|y[6][15] ;
; sdram:ram|active_dqm[1] ; Merged with sdram:ram|active_dqm[0] ;
; Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|read_byte ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[0][0] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[0][1] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[0][2] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[0][3] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[0][4] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[0][5] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[0][6] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[0][7] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[0][8] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[0][9] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[0][10] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[0][11] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[0][12] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[0][13] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[0][14] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[0][15] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[0][16] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[0][17] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[0][18] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[0][19] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[0][20] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[0][21] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[0][22] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[0][23] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter1:filter|y[0][0] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[1][0] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter1:filter|y[1][0] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[2][0] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[1][1] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[3][0] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[4][0] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[5][0] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[6][0] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[7][0] ; Stuck at GND due to stuck port data_in ;
; playrec:rc|filter4:hc|y[1][19] ; Merged with playrec:rc|filter4:hc|y[1][18] ;
; playrec:rc|filter4:hc|y[1][20] ; Merged with playrec:rc|filter4:hc|y[1][18] ;
; playrec:rc|filter4:hc|y[1][21] ; Merged with playrec:rc|filter4:hc|y[1][18] ;
; playrec:rc|filter4:hc|y[1][22] ; Merged with playrec:rc|filter4:hc|y[1][18] ;
; playrec:rc|filter4:hc|y[1][23] ; Merged with playrec:rc|filter4:hc|y[1][18] ;
; playrec:rc|filter1:filter|y[2][0] ; Merged with playrec:rc|filter3:hc1|y[0][0] ;
; playrec:rc|filter3:hc1|y[0][17] ; Merged with playrec:rc|filter3:hc1|y[0][16] ;
; playrec:rc|filter3:hc1|y[0][18] ; Merged with playrec:rc|filter3:hc1|y[0][16] ;
; playrec:rc|filter3:hc1|y[0][19] ; Merged with playrec:rc|filter3:hc1|y[0][16] ;
; playrec:rc|filter3:hc1|y[0][20] ; Merged with playrec:rc|filter3:hc1|y[0][16] ;
; playrec:rc|filter3:hc1|y[0][21] ; Merged with playrec:rc|filter3:hc1|y[0][16] ;
; playrec:rc|filter3:hc1|y[0][22] ; Merged with playrec:rc|filter3:hc1|y[0][16] ;
; playrec:rc|filter3:hc1|y[0][23] ; Merged with playrec:rc|filter3:hc1|y[0][16] ;
; playrec:rc|filter1:filter|y[0][18] ; Merged with playrec:rc|filter1:filter|y[0][17] ;
; playrec:rc|filter1:filter|y[0][19] ; Merged with playrec:rc|filter1:filter|y[0][17] ;
; playrec:rc|filter1:filter|y[0][20] ; Merged with playrec:rc|filter1:filter|y[0][17] ;
; playrec:rc|filter1:filter|y[0][21] ; Merged with playrec:rc|filter1:filter|y[0][17] ;
; playrec:rc|filter1:filter|y[0][22] ; Merged with playrec:rc|filter1:filter|y[0][17] ;
; playrec:rc|filter1:filter|y[0][23] ; Merged with playrec:rc|filter1:filter|y[0][17] ;
; playrec:rc|filter4:hc|y[7][1] ; Lost fanout ;
; playrec:rc|filter4:hc|y[7][2] ; Lost fanout ;
; playrec:rc|filter4:hc|y[7][3] ; Lost fanout ;
; playrec:rc|filter4:hc|y[7][4] ; Lost fanout ;
; playrec:rc|filter4:hc|y[7][5] ; Lost fanout ;
; playrec:rc|filter4:hc|y[7][6] ; Lost fanout ;
; playrec:rc|filter4:hc|y[7][7] ; Lost fanout ;
; playrec:rc|filter4:hc|y[1][2] ; Merged with playrec:rc|filter4:hc|y[2][1] ;
; playrec:rc|filter3:hc1|y[0][0] ; Merged with playrec:rc|filter4:hc|y[2][1] ;
; playrec:rc|filter1:filter|y[0][1] ; Merged with playrec:rc|filter4:hc|y[2][1] ;
; playrec:rc|filter1:filter|y[1][20] ; Merged with playrec:rc|filter1:filter|y[1][19] ;
; playrec:rc|filter1:filter|y[1][21] ; Merged with playrec:rc|filter1:filter|y[1][19] ;
; playrec:rc|filter1:filter|y[1][22] ; Merged with playrec:rc|filter1:filter|y[1][19] ;
; playrec:rc|filter1:filter|y[1][23] ; Merged with playrec:rc|filter1:filter|y[1][19] ;
; playrec:rc|filter3:hc1|y[1][20] ; Merged with playrec:rc|filter3:hc1|y[1][23] ;
; playrec:rc|filter3:hc1|y[1][21] ; Merged with playrec:rc|filter3:hc1|y[1][23] ;
; playrec:rc|filter3:hc1|y[1][22] ; Merged with playrec:rc|filter3:hc1|y[1][23] ;
; playrec:rc|filter4:hc|y[2][23] ; Merged with playrec:rc|filter4:hc|y[2][22] ;
; sdram:ram|m_next~9 ; Lost fanout ;
; sdram:ram|m_next~10 ; Lost fanout ;
; sdram:ram|m_next~13 ; Lost fanout ;
; sdram:ram|m_next~14 ; Lost fanout ;
; sdram:ram|m_next~16 ; Lost fanout ;
; sdram:ram|i_next~6 ; Lost fanout ;
; Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|s_alavon_slave~2 ; Lost fanout ;
; Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|s_alavon_slave~3 ; Lost fanout ;
; playrec:rc|filter1:filter|y[6][0] ; Lost fanout ;
; playrec:rc|filter4:hc|y[1][5] ; Merged with playrec:rc|filter1:filter|y[0][4] ;
; playrec:rc|filter4:hc|y[1][4] ; Merged with playrec:rc|filter1:filter|y[0][3] ;
; playrec:rc|filter4:hc|y[1][3] ; Merged with playrec:rc|filter1:filter|y[0][2] ;
; sdram:ram|active_dqm[0] ; Stuck at GND due to stuck port data_in ;
; sdram:ram|m_dqm[0,1] ; Stuck at GND due to stuck port data_in ;
; sdram:ram|m_count[2] ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 134 ; ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations ;
+---------------------------------------------------------------------------------+---------------------------+---------------------------------------------------------------+
; Register name ; Reason for Removal ; Registers Removed due to This Register ;
+---------------------------------------------------------------------------------+---------------------------+---------------------------------------------------------------+
; playrec:rc|filter4:hc|y[1][0] ; Stuck at GND ; playrec:rc|filter4:hc|y[2][0], playrec:rc|filter4:hc|y[3][0], ;
; ; due to stuck port data_in ; playrec:rc|filter4:hc|y[4][0], playrec:rc|filter4:hc|y[5][0], ;
; ; ; playrec:rc|filter4:hc|y[6][0], playrec:rc|filter4:hc|y[7][0] ;
; sdram:ram|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[16] ; Stuck at GND ; sdram:ram|active_dqm[0], sdram:ram|m_dqm[0] ;
; ; due to stuck port data_in ; ;
; sdram:ram|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[17] ; Stuck at GND ; sdram:ram|m_dqm[1] ;
; ; due to stuck port data_in ; ;
+---------------------------------------------------------------------------------+---------------------------+---------------------------------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 1239 ;
; Number of registers using Synchronous Clear ; 160 ;
; Number of registers using Synchronous Load ; 128 ;
; Number of registers using Asynchronous Clear ; 124 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 350 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+---------------------------------------------------+
; Inverted Register Statistics ;
+-----------------------------------------+---------+
; Inverted Register ; Fan out ;
+-----------------------------------------+---------+
; sdram:ram|m_cmd[0] ; 2 ;
; sdram:ram|m_cmd[1] ; 2 ;
; sdram:ram|m_cmd[2] ; 2 ;
; sdram:ram|m_cmd[3] ; 1 ;
; sdram:ram|i_addr[11] ; 10 ;
; sdram:ram|i_cmd[0] ; 2 ;
; sdram:ram|i_cmd[1] ; 2 ;
; sdram:ram|i_cmd[2] ; 2 ;
; sdram:ram|i_cmd[3] ; 2 ;
; sdram:ram|refresh_counter[12] ; 2 ;
; sdram:ram|refresh_counter[9] ; 2 ;
; sdram:ram|refresh_counter[8] ; 2 ;
; sdram:ram|refresh_counter[7] ; 2 ;
; sdram:ram|refresh_counter[3] ; 2 ;
; Total number of inverted registers = 14 ; ;
+-----------------------------------------+---------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 3:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |vr|Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|Altera_UP_I2C_AV_Auto_Initialize:Auto_Initialize|rom_address_counter[5] ;
; 3:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; Yes ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|data_in_shift_reg[10] ;
; 3:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |vr|vga_adapter:VGA|vga_controller:controller|yCounter[2] ;
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |vr|Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|Altera_UP_I2C:I2C_Controller|current_byte[4] ;
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |vr|display:disp|y[7] ;
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |vr|Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|data_to_transfer[3] ;
; 3:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |vr|Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|Altera_UP_Slow_Clock_Generator:Clock_Generator_400KHz|clk_counter[1] ;
; 4:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; Yes ; |vr|display:disp|delay_counter[9] ;
; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_Audio_Bit_Counter:Audio_Out_Bit_Counter|bit_counter[2] ;
; 4:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |vr|sdram:ram|m_dqm[0] ;
; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |vr|Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|Altera_UP_I2C:I2C_Controller|current_bit[2] ;
; 5:1 ; 9 bits ; 27 LEs ; 9 LEs ; 18 LEs ; Yes ; |vr|display:disp|x[8] ;
; 6:1 ; 4 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |vr|Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|Altera_UP_I2C_AV_Auto_Initialize:Auto_Initialize|data_out[0] ;
; 6:1 ; 4 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |vr|Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|Altera_UP_I2C_AV_Auto_Initialize:Auto_Initialize|data_out[2] ;
; 4:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |vr|sdram:ram|m_bank[1] ;
; 6:1 ; 31 bits ; 124 LEs ; 62 LEs ; 62 LEs ; Yes ; |vr|Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|data_out_shift_reg[24] ;
; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; Yes ; |vr|sdram:ram|i_count[1] ;
; 5:1 ; 22 bits ; 66 LEs ; 44 LEs ; 22 LEs ; Yes ; |vr|playrec:rc|ram_addr[15] ;
; 6:1 ; 4 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |vr|sdram:ram|m_addr[11] ;
; 7:1 ; 2 bits ; 8 LEs ; 6 LEs ; 2 LEs ; Yes ; |vr|sdram:ram|m_addr[5] ;
; 7:1 ; 6 bits ; 24 LEs ; 18 LEs ; 6 LEs ; Yes ; |vr|sdram:ram|m_addr[1] ;
; 12:1 ; 39 bits ; 312 LEs ; 0 LEs ; 312 LEs ; Yes ; |vr|sdram:ram|active_addr[12] ;
; 4:1 ; 16 bits ; 32 LEs ; 32 LEs ; 0 LEs ; Yes ; |vr|sdram:ram|m_data[3] ;
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |vr|LEDR ;
; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |vr|Mux13 ;
; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |vr|Mux13 ;
; 8:1 ; 16 bits ; 80 LEs ; 48 LEs ; 32 LEs ; No ; |vr|playrec:rc|Mux4 ;
; 12:1 ; 2 bits ; 16 LEs ; 6 LEs ; 10 LEs ; No ; |vr|playrec:rc|streg ;
; 13:1 ; 2 bits ; 16 LEs ; 6 LEs ; 10 LEs ; No ; |vr|playrec:rc|streg ;
; 13:1 ; 2 bits ; 16 LEs ; 8 LEs ; 8 LEs ; No ; |vr|playrec:rc|streg ;
; 11:1 ; 2 bits ; 14 LEs ; 4 LEs ; 10 LEs ; No ; |vr|sdram:ram|Selector34 ;
; 16:1 ; 2 bits ; 20 LEs ; 8 LEs ; 12 LEs ; No ; |vr|sdram:ram|Selector27 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
+---------------------------------------------------------------+
; Source assignments for sdram:ram ;
+-----------------------------+-------+------+------------------+
; Assignment ; Value ; From ; To ;
+-----------------------------+-------+------+------------------+
; FAST_INPUT_REGISTER ; ON ; - ; za_data[15] ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[14] ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[13] ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[12] ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[11] ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[10] ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[9] ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[8] ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[7] ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[6] ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[5] ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[4] ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[3] ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[2] ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[1] ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[0] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_cmd[3] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_cmd[2] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_cmd[1] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_cmd[0] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_bank[1] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_bank[0] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[11] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[10] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[9] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[8] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[7] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[6] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[5] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[4] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[3] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[2] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[1] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[0] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[15] ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[15] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[14] ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[14] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[13] ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[13] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[12] ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[12] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[11] ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[11] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[10] ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[10] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[9] ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[9] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[8] ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[8] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[7] ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[7] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[6] ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[6] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[5] ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[5] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[4] ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[4] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[3] ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[3] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[2] ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[2] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[1] ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[1] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[0] ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[0] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_dqm[1] ;
; FAST_OUTPUT_REGISTER ; ON ; - ; m_dqm[0] ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; oe ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[15]~reg0 ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[14]~reg0 ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[13]~reg0 ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[12]~reg0 ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[11]~reg0 ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[10]~reg0 ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[9]~reg0 ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[8]~reg0 ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[7]~reg0 ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[6]~reg0 ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[5]~reg0 ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[4]~reg0 ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[3]~reg0 ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[2]~reg0 ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[1]~reg0 ;
; FAST_INPUT_REGISTER ; ON ; - ; za_data[0]~reg0 ;
+-----------------------------+-------+------+------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+