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TimeQuest Timing Analyzer report for vr
Fri Jun 2 10:40:05 2017
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. TimeQuest Timing Analyzer Summary
3. Parallel Compilation
4. Clocks
5. Slow Model Fmax Summary
6. Slow Model Setup Summary
7. Slow Model Hold Summary
8. Slow Model Recovery Summary
9. Slow Model Removal Summary
10. Slow Model Minimum Pulse Width Summary
11. Slow Model Setup: 'CLOCK_50'
12. Slow Model Setup: 'pll|altpll_component|pll|clk[1]'
13. Slow Model Hold: 'CLOCK_50'
14. Slow Model Hold: 'pll|altpll_component|pll|clk[1]'
15. Slow Model Minimum Pulse Width: 'CLOCK_50'
16. Slow Model Minimum Pulse Width: 'pll|altpll_component|pll|clk[1]'
17. Setup Times
18. Hold Times
19. Clock to Output Times
20. Minimum Clock to Output Times
21. Propagation Delay
22. Minimum Propagation Delay
23. Output Enable Times
24. Minimum Output Enable Times
25. Output Disable Times
26. Minimum Output Disable Times
27. Fast Model Setup Summary
28. Fast Model Hold Summary
29. Fast Model Recovery Summary
30. Fast Model Removal Summary
31. Fast Model Minimum Pulse Width Summary
32. Fast Model Setup: 'CLOCK_50'
33. Fast Model Setup: 'pll|altpll_component|pll|clk[1]'
34. Fast Model Hold: 'CLOCK_50'
35. Fast Model Hold: 'pll|altpll_component|pll|clk[1]'
36. Fast Model Minimum Pulse Width: 'CLOCK_50'
37. Fast Model Minimum Pulse Width: 'pll|altpll_component|pll|clk[1]'
38. Setup Times
39. Hold Times
40. Clock to Output Times
41. Minimum Clock to Output Times
42. Propagation Delay
43. Minimum Propagation Delay
44. Output Enable Times
45. Minimum Output Enable Times
46. Output Disable Times
47. Minimum Output Disable Times
48. Multicorner Timing Analysis Summary
49. Setup Times
50. Hold Times
51. Clock to Output Times
52. Minimum Clock to Output Times
53. Progagation Delay
54. Minimum Progagation Delay
55. Setup Transfers
56. Hold Transfers
57. Report TCCS
58. Report RSKM
59. Unconstrained Paths
60. TimeQuest Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name ; vr ;
; Device Family ; Cyclone II ;
; Device Name ; EP2C35F672C6 ;
; Timing Models ; Final ;
; Delay Model ; Combined ;
; Rise/Fall Delays ; Unavailable ;
+--------------------+-------------------------------------------------------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks ;
+---------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+-----------------------------------+-------------------------------------+
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+---------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+-----------------------------------+-------------------------------------+
; CLOCK_50 ; Base ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; ; ; ; ; ; ; ; ; ; ; { CLOCK_50 } ;
; pll|altpll_component|pll|clk[0] ; Generated ; 20.000 ; 50.0 MHz ; -2.916 ; 7.084 ; 50.00 ; 1 ; 1 ; -52.5 ; ; ; ; false ; CLOCK_50 ; pll|altpll_component|pll|inclk[0] ; { pll|altpll_component|pll|clk[0] } ;
; pll|altpll_component|pll|clk[1] ; Generated ; 40.000 ; 25.0 MHz ; 0.000 ; 20.000 ; 50.00 ; 2 ; 1 ; ; ; ; ; false ; CLOCK_50 ; pll|altpll_component|pll|inclk[0] ; { pll|altpll_component|pll|clk[1] } ;
; pll|altpll_component|pll|clk[2] ; Generated ; 80.000 ; 12.5 MHz ; 0.000 ; 40.000 ; 50.00 ; 4 ; 1 ; ; ; ; ; false ; CLOCK_50 ; pll|altpll_component|pll|inclk[0] ; { pll|altpll_component|pll|clk[2] } ;
+---------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+-----------------------------------+-------------------------------------+
+----------------------------------------------------------------------+
; Slow Model Fmax Summary ;
+-----------+-----------------+---------------------------------+------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+-----------+-----------------+---------------------------------+------+
; 74.67 MHz ; 74.67 MHz ; CLOCK_50 ; ;
; 98.48 MHz ; 98.48 MHz ; pll|altpll_component|pll|clk[1] ; ;
+-----------+-----------------+---------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+----------------------------------------------------------+
; Slow Model Setup Summary ;
+---------------------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+---------------------------------+--------+---------------+
; CLOCK_50 ; 6.607 ; 0.000 ;
; pll|altpll_component|pll|clk[1] ; 29.846 ; 0.000 ;
+---------------------------------+--------+---------------+
+---------------------------------------------------------+
; Slow Model Hold Summary ;
+---------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+---------------------------------+-------+---------------+
; CLOCK_50 ; 0.391 ; 0.000 ;
; pll|altpll_component|pll|clk[1] ; 0.391 ; 0.000 ;
+---------------------------------+-------+---------------+
-------------------------------
; Slow Model Recovery Summary ;
-------------------------------
No paths to report.
------------------------------
; Slow Model Removal Summary ;
------------------------------
No paths to report.
+----------------------------------------------------------+
; Slow Model Minimum Pulse Width Summary ;
+---------------------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+---------------------------------+--------+---------------+
; CLOCK_50 ; 7.620 ; 0.000 ;
; pll|altpll_component|pll|clk[1] ; 17.873 ; 0.000 ;
+---------------------------------+--------+---------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'CLOCK_50' ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 6.607 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg0 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 13.326 ;
; 6.607 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg1 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 13.326 ;
; 6.607 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg2 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 13.326 ;
; 6.607 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg3 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 13.326 ;
; 6.607 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg4 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 13.326 ;
; 6.607 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg5 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 13.326 ;
; 6.607 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg6 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.032 ; 13.326 ;
; 6.847 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg0 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a6~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.023 ; 13.095 ;
; 6.847 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg1 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a6~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.023 ; 13.095 ;
; 6.847 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg2 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a6~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.023 ; 13.095 ;
; 6.847 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg3 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a6~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.023 ; 13.095 ;
; 6.847 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg4 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a6~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.023 ; 13.095 ;
; 6.847 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg5 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a6~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.023 ; 13.095 ;
; 6.847 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg6 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a6~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.023 ; 13.095 ;
; 6.866 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg0 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a4~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 13.072 ;
; 6.866 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg1 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a4~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 13.072 ;
; 6.866 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg2 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a4~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 13.072 ;
; 6.866 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg3 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a4~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 13.072 ;
; 6.866 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg4 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a4~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 13.072 ;
; 6.866 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg5 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a4~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 13.072 ;
; 6.866 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg6 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a4~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.027 ; 13.072 ;
; 7.075 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg0 ; playrec:rc|filter4:hc|y[3][23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.101 ; 12.860 ;
; 7.075 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg1 ; playrec:rc|filter4:hc|y[3][23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.101 ; 12.860 ;
; 7.075 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg2 ; playrec:rc|filter4:hc|y[3][23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.101 ; 12.860 ;
; 7.075 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg3 ; playrec:rc|filter4:hc|y[3][23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.101 ; 12.860 ;
; 7.075 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg4 ; playrec:rc|filter4:hc|y[3][23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.101 ; 12.860 ;
; 7.075 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg5 ; playrec:rc|filter4:hc|y[3][23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.101 ; 12.860 ;
; 7.075 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg6 ; playrec:rc|filter4:hc|y[3][23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.101 ; 12.860 ;
; 7.111 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg0 ; playrec:rc|filter1:filter|y[3][23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.093 ; 12.832 ;
; 7.111 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg1 ; playrec:rc|filter1:filter|y[3][23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.093 ; 12.832 ;
; 7.111 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg2 ; playrec:rc|filter1:filter|y[3][23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.093 ; 12.832 ;
; 7.111 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg3 ; playrec:rc|filter1:filter|y[3][23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.093 ; 12.832 ;
; 7.111 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg4 ; playrec:rc|filter1:filter|y[3][23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.093 ; 12.832 ;
; 7.111 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg5 ; playrec:rc|filter1:filter|y[3][23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.093 ; 12.832 ;
; 7.111 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg6 ; playrec:rc|filter1:filter|y[3][23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.093 ; 12.832 ;
; 7.141 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg0 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a3~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.039 ; 12.785 ;
; 7.141 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg1 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a3~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.039 ; 12.785 ;
; 7.141 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg2 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a3~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.039 ; 12.785 ;
; 7.141 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg3 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a3~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.039 ; 12.785 ;
; 7.141 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg4 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a3~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.039 ; 12.785 ;
; 7.141 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg5 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a3~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.039 ; 12.785 ;
; 7.141 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg6 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a3~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.039 ; 12.785 ;
; 7.146 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg0 ; playrec:rc|filter4:hc|y[3][22] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.101 ; 12.789 ;
; 7.146 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg1 ; playrec:rc|filter4:hc|y[3][22] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.101 ; 12.789 ;
; 7.146 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg2 ; playrec:rc|filter4:hc|y[3][22] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.101 ; 12.789 ;
; 7.146 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg3 ; playrec:rc|filter4:hc|y[3][22] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.101 ; 12.789 ;
; 7.146 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg4 ; playrec:rc|filter4:hc|y[3][22] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.101 ; 12.789 ;
; 7.146 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg5 ; playrec:rc|filter4:hc|y[3][22] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.101 ; 12.789 ;
; 7.146 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg6 ; playrec:rc|filter4:hc|y[3][22] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.101 ; 12.789 ;
; 7.151 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg0 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a16~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 12.768 ;
; 7.151 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg1 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a16~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 12.768 ;
; 7.151 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg2 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a16~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 12.768 ;
; 7.151 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg3 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a16~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 12.768 ;
; 7.151 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg4 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a16~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 12.768 ;
; 7.151 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg5 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a16~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 12.768 ;
; 7.151 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg6 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a16~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 12.768 ;
; 7.166 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg0 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a9~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 12.743 ;
; 7.166 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg1 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a9~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 12.743 ;
; 7.166 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg2 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a9~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 12.743 ;
; 7.166 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg3 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a9~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 12.743 ;
; 7.166 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg4 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a9~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 12.743 ;
; 7.166 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg5 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a9~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 12.743 ;
; 7.166 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg6 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a9~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 12.743 ;
; 7.192 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg0 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a13~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 12.715 ;
; 7.192 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg1 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a13~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 12.715 ;
; 7.192 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg2 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a13~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 12.715 ;
; 7.192 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg3 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a13~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 12.715 ;
; 7.192 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg4 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a13~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 12.715 ;
; 7.192 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg5 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a13~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 12.715 ;
; 7.192 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg6 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a13~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.058 ; 12.715 ;
; 7.217 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg0 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a5~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.045 ; 12.703 ;
; 7.217 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg1 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a5~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.045 ; 12.703 ;
; 7.217 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg2 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a5~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.045 ; 12.703 ;
; 7.217 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg3 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a5~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.045 ; 12.703 ;
; 7.217 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg4 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a5~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.045 ; 12.703 ;
; 7.217 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg5 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a5~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.045 ; 12.703 ;
; 7.217 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg6 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a5~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.045 ; 12.703 ;
; 7.229 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg0 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a7~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.067 ; 12.669 ;
; 7.229 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg1 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a7~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.067 ; 12.669 ;
; 7.229 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg2 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a7~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.067 ; 12.669 ;
; 7.229 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg3 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a7~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.067 ; 12.669 ;
; 7.229 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg4 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a7~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.067 ; 12.669 ;
; 7.229 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg5 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a7~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.067 ; 12.669 ;
; 7.229 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg6 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a7~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.067 ; 12.669 ;
; 7.245 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg0 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a15~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 12.664 ;
; 7.245 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg1 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a15~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 12.664 ;
; 7.245 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg2 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a15~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 12.664 ;
; 7.245 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg3 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a15~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 12.664 ;
; 7.245 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg4 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a15~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 12.664 ;
; 7.245 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg5 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a15~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 12.664 ;
; 7.245 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg6 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a15~portb_datain_reg0 ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 12.664 ;
; 7.374 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg0 ; playrec:rc|filter1:filter|y[7][23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.110 ; 12.552 ;
; 7.374 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg1 ; playrec:rc|filter1:filter|y[7][23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.110 ; 12.552 ;
; 7.374 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg2 ; playrec:rc|filter1:filter|y[7][23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.110 ; 12.552 ;
; 7.374 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg3 ; playrec:rc|filter1:filter|y[7][23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.110 ; 12.552 ;
; 7.374 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg4 ; playrec:rc|filter1:filter|y[7][23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.110 ; 12.552 ;
; 7.374 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg5 ; playrec:rc|filter1:filter|y[7][23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.110 ; 12.552 ;
; 7.374 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg6 ; playrec:rc|filter1:filter|y[7][23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.110 ; 12.552 ;
; 7.445 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg0 ; playrec:rc|filter1:filter|y[7][22] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.110 ; 12.481 ;
; 7.445 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|altsyncram_rc81:FIFOram|ram_block1a16~portb_address_reg1 ; playrec:rc|filter1:filter|y[7][22] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.110 ; 12.481 ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'pll|altpll_component|pll|clk[1]' ;
+--------+-------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+---------------------------------+---------------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+---------------------------------+---------------------------------+--------------+------------+------------+
; 29.846 ; vga_adapter:VGA|vga_controller:controller|yCounter[4] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg11 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 10.195 ;
; 29.846 ; vga_adapter:VGA|vga_controller:controller|yCounter[4] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg10 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 10.195 ;
; 29.846 ; vga_adapter:VGA|vga_controller:controller|yCounter[4] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg9 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 10.195 ;
; 29.846 ; vga_adapter:VGA|vga_controller:controller|yCounter[4] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg8 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 10.195 ;
; 29.846 ; vga_adapter:VGA|vga_controller:controller|yCounter[4] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg7 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 10.195 ;
; 29.846 ; vga_adapter:VGA|vga_controller:controller|yCounter[4] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg6 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 10.195 ;
; 29.846 ; vga_adapter:VGA|vga_controller:controller|yCounter[4] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg5 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 10.195 ;
; 29.846 ; vga_adapter:VGA|vga_controller:controller|yCounter[4] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg4 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 10.195 ;
; 29.846 ; vga_adapter:VGA|vga_controller:controller|yCounter[4] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg3 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 10.195 ;
; 29.846 ; vga_adapter:VGA|vga_controller:controller|yCounter[4] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg2 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 10.195 ;
; 29.846 ; vga_adapter:VGA|vga_controller:controller|yCounter[4] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg1 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 10.195 ;
; 29.846 ; vga_adapter:VGA|vga_controller:controller|yCounter[4] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg0 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 10.195 ;
; 30.036 ; vga_adapter:VGA|vga_controller:controller|yCounter[2] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg11 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 10.004 ;
; 30.036 ; vga_adapter:VGA|vga_controller:controller|yCounter[2] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg10 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 10.004 ;
; 30.036 ; vga_adapter:VGA|vga_controller:controller|yCounter[2] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg9 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 10.004 ;
; 30.036 ; vga_adapter:VGA|vga_controller:controller|yCounter[2] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg8 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 10.004 ;
; 30.036 ; vga_adapter:VGA|vga_controller:controller|yCounter[2] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg7 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 10.004 ;
; 30.036 ; vga_adapter:VGA|vga_controller:controller|yCounter[2] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg6 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 10.004 ;
; 30.036 ; vga_adapter:VGA|vga_controller:controller|yCounter[2] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg5 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 10.004 ;
; 30.036 ; vga_adapter:VGA|vga_controller:controller|yCounter[2] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg4 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 10.004 ;
; 30.036 ; vga_adapter:VGA|vga_controller:controller|yCounter[2] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg3 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 10.004 ;
; 30.036 ; vga_adapter:VGA|vga_controller:controller|yCounter[2] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg2 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 10.004 ;
; 30.036 ; vga_adapter:VGA|vga_controller:controller|yCounter[2] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg1 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 10.004 ;
; 30.036 ; vga_adapter:VGA|vga_controller:controller|yCounter[2] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg0 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 10.004 ;
; 30.196 ; vga_adapter:VGA|vga_controller:controller|yCounter[3] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg11 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.845 ;
; 30.196 ; vga_adapter:VGA|vga_controller:controller|yCounter[3] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg10 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.845 ;
; 30.196 ; vga_adapter:VGA|vga_controller:controller|yCounter[3] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg9 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.845 ;
; 30.196 ; vga_adapter:VGA|vga_controller:controller|yCounter[3] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg8 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.845 ;
; 30.196 ; vga_adapter:VGA|vga_controller:controller|yCounter[3] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg7 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.845 ;
; 30.196 ; vga_adapter:VGA|vga_controller:controller|yCounter[3] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg6 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.845 ;
; 30.196 ; vga_adapter:VGA|vga_controller:controller|yCounter[3] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg5 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.845 ;
; 30.196 ; vga_adapter:VGA|vga_controller:controller|yCounter[3] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg4 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.845 ;
; 30.196 ; vga_adapter:VGA|vga_controller:controller|yCounter[3] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg3 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.845 ;
; 30.196 ; vga_adapter:VGA|vga_controller:controller|yCounter[3] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg2 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.845 ;
; 30.196 ; vga_adapter:VGA|vga_controller:controller|yCounter[3] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg1 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.845 ;
; 30.196 ; vga_adapter:VGA|vga_controller:controller|yCounter[3] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg0 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.845 ;
; 30.235 ; vga_adapter:VGA|vga_controller:controller|yCounter[1] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg11 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.806 ;
; 30.235 ; vga_adapter:VGA|vga_controller:controller|yCounter[1] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg10 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.806 ;
; 30.235 ; vga_adapter:VGA|vga_controller:controller|yCounter[1] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg9 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.806 ;
; 30.235 ; vga_adapter:VGA|vga_controller:controller|yCounter[1] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg8 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.806 ;
; 30.235 ; vga_adapter:VGA|vga_controller:controller|yCounter[1] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg7 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.806 ;
; 30.235 ; vga_adapter:VGA|vga_controller:controller|yCounter[1] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg6 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.806 ;
; 30.235 ; vga_adapter:VGA|vga_controller:controller|yCounter[1] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg5 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.806 ;
; 30.235 ; vga_adapter:VGA|vga_controller:controller|yCounter[1] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg4 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.806 ;
; 30.235 ; vga_adapter:VGA|vga_controller:controller|yCounter[1] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg3 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.806 ;
; 30.235 ; vga_adapter:VGA|vga_controller:controller|yCounter[1] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg2 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.806 ;
; 30.235 ; vga_adapter:VGA|vga_controller:controller|yCounter[1] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg1 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.806 ;
; 30.235 ; vga_adapter:VGA|vga_controller:controller|yCounter[1] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg0 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.806 ;
; 30.264 ; vga_adapter:VGA|vga_controller:controller|yCounter[7] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg11 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 9.776 ;
; 30.264 ; vga_adapter:VGA|vga_controller:controller|yCounter[7] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg10 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 9.776 ;
; 30.264 ; vga_adapter:VGA|vga_controller:controller|yCounter[7] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg9 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 9.776 ;
; 30.264 ; vga_adapter:VGA|vga_controller:controller|yCounter[7] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg8 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 9.776 ;
; 30.264 ; vga_adapter:VGA|vga_controller:controller|yCounter[7] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg7 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 9.776 ;
; 30.264 ; vga_adapter:VGA|vga_controller:controller|yCounter[7] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg6 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 9.776 ;
; 30.264 ; vga_adapter:VGA|vga_controller:controller|yCounter[7] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg5 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 9.776 ;
; 30.264 ; vga_adapter:VGA|vga_controller:controller|yCounter[7] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg4 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 9.776 ;
; 30.264 ; vga_adapter:VGA|vga_controller:controller|yCounter[7] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg3 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 9.776 ;
; 30.264 ; vga_adapter:VGA|vga_controller:controller|yCounter[7] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg2 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 9.776 ;
; 30.264 ; vga_adapter:VGA|vga_controller:controller|yCounter[7] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg1 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 9.776 ;
; 30.264 ; vga_adapter:VGA|vga_controller:controller|yCounter[7] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg0 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 9.776 ;
; 30.354 ; vga_adapter:VGA|vga_controller:controller|yCounter[8] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg11 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 9.686 ;
; 30.354 ; vga_adapter:VGA|vga_controller:controller|yCounter[8] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg10 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 9.686 ;
; 30.354 ; vga_adapter:VGA|vga_controller:controller|yCounter[8] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg9 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 9.686 ;
; 30.354 ; vga_adapter:VGA|vga_controller:controller|yCounter[8] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg8 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 9.686 ;
; 30.354 ; vga_adapter:VGA|vga_controller:controller|yCounter[8] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg7 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 9.686 ;
; 30.354 ; vga_adapter:VGA|vga_controller:controller|yCounter[8] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg6 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 9.686 ;
; 30.354 ; vga_adapter:VGA|vga_controller:controller|yCounter[8] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg5 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 9.686 ;
; 30.354 ; vga_adapter:VGA|vga_controller:controller|yCounter[8] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg4 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 9.686 ;
; 30.354 ; vga_adapter:VGA|vga_controller:controller|yCounter[8] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg3 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 9.686 ;
; 30.354 ; vga_adapter:VGA|vga_controller:controller|yCounter[8] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg2 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 9.686 ;
; 30.354 ; vga_adapter:VGA|vga_controller:controller|yCounter[8] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg1 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 9.686 ;
; 30.354 ; vga_adapter:VGA|vga_controller:controller|yCounter[8] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg0 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.075 ; 9.686 ;
; 30.411 ; vga_adapter:VGA|vga_controller:controller|yCounter[5] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg11 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.630 ;
; 30.411 ; vga_adapter:VGA|vga_controller:controller|yCounter[5] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg10 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.630 ;
; 30.411 ; vga_adapter:VGA|vga_controller:controller|yCounter[5] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg9 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.630 ;
; 30.411 ; vga_adapter:VGA|vga_controller:controller|yCounter[5] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg8 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.630 ;
; 30.411 ; vga_adapter:VGA|vga_controller:controller|yCounter[5] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg7 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.630 ;
; 30.411 ; vga_adapter:VGA|vga_controller:controller|yCounter[5] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg6 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.630 ;
; 30.411 ; vga_adapter:VGA|vga_controller:controller|yCounter[5] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg5 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.630 ;
; 30.411 ; vga_adapter:VGA|vga_controller:controller|yCounter[5] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg4 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.630 ;
; 30.411 ; vga_adapter:VGA|vga_controller:controller|yCounter[5] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg3 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.630 ;
; 30.411 ; vga_adapter:VGA|vga_controller:controller|yCounter[5] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg2 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.630 ;
; 30.411 ; vga_adapter:VGA|vga_controller:controller|yCounter[5] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg1 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.630 ;
; 30.411 ; vga_adapter:VGA|vga_controller:controller|yCounter[5] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg0 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.630 ;
; 30.448 ; vga_adapter:VGA|vga_controller:controller|yCounter[6] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg11 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.593 ;
; 30.448 ; vga_adapter:VGA|vga_controller:controller|yCounter[6] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg10 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.593 ;
; 30.448 ; vga_adapter:VGA|vga_controller:controller|yCounter[6] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg9 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.593 ;
; 30.448 ; vga_adapter:VGA|vga_controller:controller|yCounter[6] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg8 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.593 ;
; 30.448 ; vga_adapter:VGA|vga_controller:controller|yCounter[6] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg7 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.593 ;
; 30.448 ; vga_adapter:VGA|vga_controller:controller|yCounter[6] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg6 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.593 ;
; 30.448 ; vga_adapter:VGA|vga_controller:controller|yCounter[6] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg5 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.593 ;
; 30.448 ; vga_adapter:VGA|vga_controller:controller|yCounter[6] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg4 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.593 ;
; 30.448 ; vga_adapter:VGA|vga_controller:controller|yCounter[6] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg3 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.593 ;
; 30.448 ; vga_adapter:VGA|vga_controller:controller|yCounter[6] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg2 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.593 ;
; 30.448 ; vga_adapter:VGA|vga_controller:controller|yCounter[6] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg1 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.593 ;
; 30.448 ; vga_adapter:VGA|vga_controller:controller|yCounter[6] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a14~porta_address_reg0 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.076 ; 9.593 ;
; 30.856 ; vga_adapter:VGA|vga_controller:controller|yCounter[2] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a17~porta_address_reg11 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.060 ; 9.169 ;
; 30.856 ; vga_adapter:VGA|vga_controller:controller|yCounter[2] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a17~porta_address_reg10 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.060 ; 9.169 ;
; 30.856 ; vga_adapter:VGA|vga_controller:controller|yCounter[2] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a17~porta_address_reg9 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.060 ; 9.169 ;
; 30.856 ; vga_adapter:VGA|vga_controller:controller|yCounter[2] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a17~porta_address_reg8 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 40.000 ; 0.060 ; 9.169 ;
+--------+-------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+---------------------------------+---------------------------------+--------------+------------+------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'CLOCK_50' ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.391 ; Audio_Controller:Audio_Controller|done_adc_channel_sync ; Audio_Controller:Audio_Controller|done_adc_channel_sync ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|wr_address ; sdram:ram|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|wr_address ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|i_count[1] ; sdram:ram|i_count[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|i_count[0] ; sdram:ram|i_count[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|i_count[2] ; sdram:ram|i_count[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|i_refs[0] ; sdram:ram|i_refs[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|i_refs[1] ; sdram:ram|i_refs[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|i_refs[2] ; sdram:ram|i_refs[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|i_next~5 ; sdram:ram|i_next~5 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|i_state~15 ; sdram:ram|i_state~15 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|i_state~16 ; sdram:ram|i_state~16 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|init_done ; sdram:ram|init_done ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|m_count[1] ; sdram:ram|m_count[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|m_state~18 ; sdram:ram|m_state~18 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_rnw ; sdram:ram|active_rnw ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|m_next~12 ; sdram:ram|m_next~12 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|m_state~17 ; sdram:ram|m_state~17 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_address ; sdram:ram|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_address ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|m_next~11 ; sdram:ram|m_next~11 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|m_state~16 ; sdram:ram|m_state~16 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|m_next~15 ; sdram:ram|m_next~15 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|ack_refresh_request ; sdram:ram|ack_refresh_request ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|refresh_request ; sdram:ram|refresh_request ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_addr[14] ; sdram:ram|active_addr[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_addr[15] ; sdram:ram|active_addr[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_addr[16] ; sdram:ram|active_addr[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_addr[17] ; sdram:ram|active_addr[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_addr[10] ; sdram:ram|active_addr[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_addr[12] ; sdram:ram|active_addr[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_addr[11] ; sdram:ram|active_addr[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_addr[13] ; sdram:ram|active_addr[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_addr[9] ; sdram:ram|active_addr[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_addr[8] ; sdram:ram|active_addr[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_addr[21] ; sdram:ram|active_addr[21] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_addr[18] ; sdram:ram|active_addr[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_cs_n ; sdram:ram|active_cs_n ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_addr[20] ; sdram:ram|active_addr[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_addr[19] ; sdram:ram|active_addr[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entries[1] ; sdram:ram|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entries[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entries[0] ; sdram:ram|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entries[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; playrec:rc|streg~4 ; playrec:rc|streg~4 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|usedw_is_2_dff ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|usedw_is_2_dff ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|usedw_is_1_dff ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|usedw_is_1_dff ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|full_dff ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|full_dff ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|usedw_is_1_dff ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|usedw_is_1_dff ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|usedw_is_2_dff ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|usedw_is_2_dff ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|full_dff ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|full_dff ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|done_dac_channel_sync ; Audio_Controller:Audio_Controller|done_dac_channel_sync ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|full_dff ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|full_dff ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|i_cmd[2] ; sdram:ram|i_cmd[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|i_cmd[0] ; sdram:ram|i_cmd[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|i_cmd[1] ; sdram:ram|i_cmd[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|left_channel_was_read ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|left_channel_was_read ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|full_dff ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|full_dff ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; blink_cnt[0] ; blink_cnt[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_Audio_Bit_Counter:Audio_Out_Bit_Counter|counting ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_Audio_Bit_Counter:Audio_Out_Bit_Counter|counting ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|rd_ptr_lsb ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|rd_ptr_lsb ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[6] ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[5] ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[4] ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[3] ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[2] ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[1] ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[0] ; Audio_Controller:Audio_Controller|Altera_UP_Audio_In_Deserializer:Audio_In_Deserializer|Altera_UP_SYNC_FIFO:Audio_In_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_data[15] ; sdram:ram|active_data[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_data[10] ; sdram:ram|active_data[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_data[6] ; sdram:ram|active_data[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_data[14] ; sdram:ram|active_data[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_data[8] ; sdram:ram|active_data[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_data[12] ; sdram:ram|active_data[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_data[4] ; sdram:ram|active_data[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_data[11] ; sdram:ram|active_data[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_data[3] ; sdram:ram|active_data[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_data[7] ; sdram:ram|active_data[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_data[9] ; sdram:ram|active_data[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_data[5] ; sdram:ram|active_data[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_data[13] ; sdram:ram|active_data[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_data[2] ; sdram:ram|active_data[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_data[1] ; sdram:ram|active_data[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; sdram:ram|active_data[0] ; sdram:ram|active_data[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|rd_ptr_lsb ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|rd_ptr_lsb ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[6] ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[5] ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[4] ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[3] ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[2] ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[1] ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[0] ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Left_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|rd_ptr_lsb ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|rd_ptr_lsb ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[6] ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[5] ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[4] ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[3] ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[2] ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[1] ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[0] ; Audio_Controller:Audio_Controller|Altera_UP_Audio_Out_Serializer:Audio_Out_Serializer|Altera_UP_SYNC_FIFO:Audio_Out_Right_Channel_FIFO|scfifo:Sync_FIFO|scfifo_5041:auto_generated|a_dpfifo_on31:dpfifo|low_addressa[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|Altera_UP_I2C_AV_Auto_Initialize:Auto_Initialize|send_stop_bit ; Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|Altera_UP_I2C_AV_Auto_Initialize:Auto_Initialize|send_stop_bit ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|Altera_UP_I2C_AV_Auto_Initialize:Auto_Initialize|send_start_bit ; Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|Altera_UP_I2C_AV_Auto_Initialize:Auto_Initialize|send_start_bit ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|num_bits_to_transfer[0] ; Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|num_bits_to_transfer[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|Altera_UP_I2C:I2C_Controller|current_bit[0] ; Audio_Controller:Audio_Controller|Audio_and_Video_Config:Audio_Config|Altera_UP_I2C:I2C_Controller|current_bit[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.000 ; 0.657 ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'pll|altpll_component|pll|clk[1]' ;
+-------+--------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+---------------------------------+---------------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+---------------------------------+---------------------------------+--------------+------------+------------+
; 0.391 ; vga_adapter:VGA|vga_controller:controller|yCounter[2] ; vga_adapter:VGA|vga_controller:controller|yCounter[2] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; vga_adapter:VGA|vga_controller:controller|yCounter[3] ; vga_adapter:VGA|vga_controller:controller|yCounter[3] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; vga_adapter:VGA|vga_controller:controller|yCounter[4] ; vga_adapter:VGA|vga_controller:controller|yCounter[4] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; vga_adapter:VGA|vga_controller:controller|yCounter[5] ; vga_adapter:VGA|vga_controller:controller|yCounter[5] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; vga_adapter:VGA|vga_controller:controller|yCounter[6] ; vga_adapter:VGA|vga_controller:controller|yCounter[6] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; vga_adapter:VGA|vga_controller:controller|yCounter[7] ; vga_adapter:VGA|vga_controller:controller|yCounter[7] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; vga_adapter:VGA|vga_controller:controller|yCounter[8] ; vga_adapter:VGA|vga_controller:controller|yCounter[8] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; vga_adapter:VGA|vga_controller:controller|yCounter[9] ; vga_adapter:VGA|vga_controller:controller|yCounter[9] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; vga_adapter:VGA|vga_controller:controller|yCounter[0] ; vga_adapter:VGA|vga_controller:controller|yCounter[0] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; vga_adapter:VGA|vga_controller:controller|yCounter[1] ; vga_adapter:VGA|vga_controller:controller|yCounter[1] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 0.657 ;
; 0.518 ; vga_adapter:VGA|vga_controller:controller|VGA_BLANK1 ; vga_adapter:VGA|vga_controller:controller|VGA_BLANK ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 0.784 ;
; 0.524 ; vga_adapter:VGA|vga_controller:controller|VGA_HS1 ; vga_adapter:VGA|vga_controller:controller|VGA_HS ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 0.790 ;
; 0.529 ; vga_adapter:VGA|vga_controller:controller|yCounter[9] ; vga_adapter:VGA|vga_controller:controller|VGA_BLANK1 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 0.795 ;
; 0.764 ; vga_adapter:VGA|vga_controller:controller|yCounter[1] ; vga_adapter:VGA|vga_controller:controller|VGA_VS1 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; -0.002 ; 1.028 ;
; 0.812 ; vga_adapter:VGA|vga_controller:controller|xCounter[4] ; vga_adapter:VGA|vga_controller:controller|xCounter[4] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.078 ;
; 0.817 ; vga_adapter:VGA|vga_controller:controller|xCounter[2] ; vga_adapter:VGA|vga_controller:controller|xCounter[2] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.083 ;
; 0.820 ; vga_adapter:VGA|vga_controller:controller|xCounter[6] ; vga_adapter:VGA|vga_controller:controller|xCounter[6] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.086 ;
; 0.826 ; vga_adapter:VGA|vga_controller:controller|xCounter[8] ; vga_adapter:VGA|vga_controller:controller|VGA_HS1 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.092 ;
; 0.851 ; vga_adapter:VGA|vga_controller:controller|xCounter[9] ; vga_adapter:VGA|vga_controller:controller|VGA_BLANK1 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.117 ;
; 0.851 ; vga_adapter:VGA|vga_controller:controller|xCounter[9] ; vga_adapter:VGA|vga_controller:controller|VGA_HS1 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.117 ;
; 0.852 ; vga_adapter:VGA|vga_controller:controller|xCounter[7] ; vga_adapter:VGA|vga_controller:controller|xCounter[7] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.118 ;
; 0.853 ; vga_adapter:VGA|vga_controller:controller|xCounter[3] ; vga_adapter:VGA|vga_controller:controller|xCounter[3] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.119 ;
; 0.854 ; vga_adapter:VGA|vga_controller:controller|xCounter[0] ; vga_adapter:VGA|vga_controller:controller|xCounter[0] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.120 ;
; 0.860 ; vga_adapter:VGA|vga_controller:controller|xCounter[1] ; vga_adapter:VGA|vga_controller:controller|xCounter[1] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.126 ;
; 0.979 ; vga_adapter:VGA|vga_controller:controller|VGA_VS1 ; vga_adapter:VGA|vga_controller:controller|VGA_VS ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.007 ; 1.252 ;
; 1.000 ; vga_adapter:VGA|vga_controller:controller|xCounter[7] ; vga_adapter:VGA|vga_controller:controller|VGA_HS1 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; -0.004 ; 1.262 ;
; 1.027 ; vga_adapter:VGA|vga_controller:controller|yCounter[0] ; vga_adapter:VGA|vga_controller:controller|VGA_VS1 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; -0.002 ; 1.291 ;
; 1.072 ; vga_adapter:VGA|vga_controller:controller|xCounter[2] ; vga_adapter:VGA|vga_controller:controller|xCounter[5] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.338 ;
; 1.115 ; vga_adapter:VGA|vga_controller:controller|xCounter[5] ; vga_adapter:VGA|vga_controller:controller|VGA_HS1 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; -0.004 ; 1.377 ;
; 1.199 ; vga_adapter:VGA|vga_controller:controller|xCounter[5] ; vga_adapter:VGA|vga_controller:controller|xCounter[6] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.465 ;
; 1.203 ; vga_adapter:VGA|vga_controller:controller|xCounter[6] ; vga_adapter:VGA|vga_controller:controller|xCounter[7] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.469 ;
; 1.229 ; vga_adapter:VGA|vga_controller:controller|xCounter[3] ; vga_adapter:VGA|vga_controller:controller|xCounter[5] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.495 ;
; 1.239 ; vga_adapter:VGA|vga_controller:controller|xCounter[3] ; vga_adapter:VGA|vga_controller:controller|xCounter[4] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.505 ;
; 1.240 ; vga_adapter:VGA|vga_controller:controller|xCounter[0] ; vga_adapter:VGA|vga_controller:controller|xCounter[1] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.506 ;
; 1.246 ; vga_adapter:VGA|vga_controller:controller|xCounter[1] ; vga_adapter:VGA|vga_controller:controller|xCounter[2] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.512 ;
; 1.266 ; vga_adapter:VGA|vga_controller:controller|xCounter[4] ; vga_adapter:VGA|vga_controller:controller|xCounter[6] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.532 ;
; 1.270 ; vga_adapter:VGA|vga_controller:controller|xCounter[5] ; vga_adapter:VGA|vga_controller:controller|xCounter[7] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.536 ;
; 1.292 ; vga_adapter:VGA|vga_controller:controller|xCounter[2] ; vga_adapter:VGA|vga_controller:controller|xCounter[3] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.558 ;
; 1.311 ; vga_adapter:VGA|vga_controller:controller|xCounter[0] ; vga_adapter:VGA|vga_controller:controller|xCounter[2] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.577 ;
; 1.337 ; vga_adapter:VGA|vga_controller:controller|xCounter[4] ; vga_adapter:VGA|vga_controller:controller|xCounter[7] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.603 ;
; 1.362 ; vga_adapter:VGA|vga_controller:controller|xCounter[5] ; vga_adapter:VGA|vga_controller:controller|xCounter[5] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.628 ;
; 1.363 ; vga_adapter:VGA|vga_controller:controller|xCounter[2] ; vga_adapter:VGA|vga_controller:controller|xCounter[4] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.629 ;
; 1.366 ; vga_adapter:VGA|vga_controller:controller|xCounter[1] ; vga_adapter:VGA|vga_controller:controller|xCounter[5] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.632 ;
; 1.375 ; vga_adapter:VGA|vga_controller:controller|xCounter[6] ; vga_adapter:VGA|vga_controller:controller|VGA_HS1 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; -0.004 ; 1.637 ;
; 1.381 ; vga_adapter:VGA|vga_controller:controller|xCounter[3] ; vga_adapter:VGA|vga_controller:controller|xCounter[6] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.647 ;
; 1.391 ; vga_adapter:VGA|vga_controller:controller|xCounter[7] ; vga_adapter:VGA|vga_controller:controller|VGA_BLANK1 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; -0.004 ; 1.653 ;
; 1.402 ; vga_adapter:VGA|vga_controller:controller|xCounter[1] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~porta_address_reg0 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.079 ; 1.715 ;
; 1.405 ; vga_adapter:VGA|vga_controller:controller|xCounter[1] ; vga_adapter:VGA|vga_controller:controller|xCounter[3] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.671 ;
; 1.434 ; vga_adapter:VGA|vga_controller:controller|xCounter[8] ; vga_adapter:VGA|vga_controller:controller|VGA_BLANK1 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.700 ;
; 1.452 ; vga_adapter:VGA|vga_controller:controller|xCounter[3] ; vga_adapter:VGA|vga_controller:controller|xCounter[7] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.718 ;
; 1.470 ; vga_adapter:VGA|vga_controller:controller|xCounter[0] ; vga_adapter:VGA|vga_controller:controller|xCounter[3] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.736 ;
; 1.476 ; vga_adapter:VGA|vga_controller:controller|xCounter[1] ; vga_adapter:VGA|vga_controller:controller|xCounter[4] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.742 ;
; 1.505 ; vga_adapter:VGA|vga_controller:controller|xCounter[2] ; vga_adapter:VGA|vga_controller:controller|xCounter[6] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.771 ;
; 1.541 ; vga_adapter:VGA|vga_controller:controller|xCounter[0] ; vga_adapter:VGA|vga_controller:controller|xCounter[4] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.807 ;
; 1.560 ; vga_adapter:VGA|vga_controller:controller|xCounter[2] ; vga_adapter:VGA|vga_controller:controller|yCounter[4] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; -0.005 ; 1.821 ;
; 1.563 ; vga_adapter:VGA|vga_controller:controller|xCounter[2] ; vga_adapter:VGA|vga_controller:controller|yCounter[5] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; -0.005 ; 1.824 ;
; 1.564 ; vga_adapter:VGA|vga_controller:controller|xCounter[2] ; vga_adapter:VGA|vga_controller:controller|yCounter[3] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; -0.005 ; 1.825 ;
; 1.564 ; vga_adapter:VGA|vga_controller:controller|xCounter[2] ; vga_adapter:VGA|vga_controller:controller|yCounter[1] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; -0.005 ; 1.825 ;
; 1.566 ; vga_adapter:VGA|vga_controller:controller|xCounter[2] ; vga_adapter:VGA|vga_controller:controller|yCounter[6] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; -0.005 ; 1.827 ;
; 1.566 ; vga_adapter:VGA|vga_controller:controller|xCounter[2] ; vga_adapter:VGA|vga_controller:controller|yCounter[0] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; -0.005 ; 1.827 ;
; 1.576 ; vga_adapter:VGA|vga_controller:controller|xCounter[2] ; vga_adapter:VGA|vga_controller:controller|xCounter[7] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.842 ;
; 1.583 ; vga_adapter:VGA|vga_controller:controller|xCounter[9] ; vga_adapter:VGA|vga_controller:controller|xCounter[9] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.849 ;
; 1.590 ; vga_adapter:VGA|vga_controller:controller|xCounter[4] ; vga_adapter:VGA|vga_controller:controller|xCounter[5] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.856 ;
; 1.598 ; vga_adapter:VGA|vga_controller:controller|xCounter[4] ; vga_adapter:VGA|vga_controller:controller|VGA_HS1 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; -0.004 ; 1.860 ;
; 1.608 ; vga_adapter:VGA|vga_controller:controller|xCounter[3] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~porta_address_reg2 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.079 ; 1.921 ;
; 1.618 ; vga_adapter:VGA|vga_controller:controller|xCounter[1] ; vga_adapter:VGA|vga_controller:controller|xCounter[6] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.884 ;
; 1.637 ; vga_adapter:VGA|vga_controller:controller|xCounter[0] ; vga_adapter:VGA|vga_controller:controller|xCounter[5] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.903 ;
; 1.662 ; vga_adapter:VGA|vga_controller:controller|xCounter[6] ; vga_adapter:VGA|vga_controller:controller|xCounter[5] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.928 ;
; 1.678 ; vga_adapter:VGA|vga_controller:controller|xCounter[3] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a4~porta_address_reg2 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.076 ; 1.988 ;
; 1.682 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|address_reg_a[3] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|out_address_reg_a[3] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.005 ; 1.953 ;
; 1.682 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|address_reg_a[0] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|out_address_reg_a[0] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.005 ; 1.953 ;
; 1.683 ; vga_adapter:VGA|vga_controller:controller|xCounter[0] ; vga_adapter:VGA|vga_controller:controller|xCounter[6] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.949 ;
; 1.689 ; vga_adapter:VGA|vga_controller:controller|xCounter[1] ; vga_adapter:VGA|vga_controller:controller|xCounter[7] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.955 ;
; 1.692 ; vga_adapter:VGA|vga_controller:controller|xCounter[2] ; vga_adapter:VGA|vga_controller:controller|xCounter[9] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; -0.004 ; 1.954 ;
; 1.695 ; vga_adapter:VGA|vga_controller:controller|yCounter[5] ; vga_adapter:VGA|vga_controller:controller|VGA_VS1 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; -0.002 ; 1.959 ;
; 1.701 ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|address_reg_a[4] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|out_address_reg_a[4] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.005 ; 1.972 ;
; 1.704 ; vga_adapter:VGA|vga_controller:controller|xCounter[1] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a2~porta_address_reg0 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.073 ; 2.011 ;
; 1.707 ; vga_adapter:VGA|vga_controller:controller|yCounter[8] ; vga_adapter:VGA|vga_controller:controller|VGA_VS1 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; -0.003 ; 1.970 ;
; 1.717 ; vga_adapter:VGA|vga_controller:controller|xCounter[3] ; vga_adapter:VGA|vga_controller:controller|yCounter[4] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; -0.005 ; 1.978 ;
; 1.719 ; vga_adapter:VGA|vga_controller:controller|xCounter[3] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a2~porta_address_reg2 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.073 ; 2.026 ;
; 1.720 ; vga_adapter:VGA|vga_controller:controller|xCounter[3] ; vga_adapter:VGA|vga_controller:controller|yCounter[5] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; -0.005 ; 1.981 ;
; 1.721 ; vga_adapter:VGA|vga_controller:controller|xCounter[3] ; vga_adapter:VGA|vga_controller:controller|yCounter[3] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; -0.005 ; 1.982 ;
; 1.721 ; vga_adapter:VGA|vga_controller:controller|xCounter[3] ; vga_adapter:VGA|vga_controller:controller|yCounter[1] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; -0.005 ; 1.982 ;
; 1.723 ; vga_adapter:VGA|vga_controller:controller|xCounter[3] ; vga_adapter:VGA|vga_controller:controller|yCounter[6] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; -0.005 ; 1.984 ;
; 1.723 ; vga_adapter:VGA|vga_controller:controller|xCounter[3] ; vga_adapter:VGA|vga_controller:controller|yCounter[0] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; -0.005 ; 1.984 ;
; 1.729 ; vga_adapter:VGA|vga_controller:controller|xCounter[7] ; vga_adapter:VGA|vga_controller:controller|xCounter[5] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 1.995 ;
; 1.734 ; vga_adapter:VGA|vga_controller:controller|xCounter[3] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a1~porta_address_reg2 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.067 ; 2.035 ;
; 1.752 ; vga_adapter:VGA|vga_controller:controller|xCounter[8] ; vga_adapter:VGA|vga_controller:controller|xCounter[8] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 2.018 ;
; 1.752 ; vga_adapter:VGA|vga_controller:controller|xCounter[1] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a1~porta_address_reg0 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.067 ; 2.053 ;
; 1.754 ; vga_adapter:VGA|vga_controller:controller|xCounter[0] ; vga_adapter:VGA|vga_controller:controller|xCounter[7] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.000 ; 2.020 ;
; 1.755 ; vga_adapter:VGA|vga_controller:controller|xCounter[3] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a3~porta_address_reg2 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.064 ; 2.053 ;
; 1.764 ; vga_adapter:VGA|vga_controller:controller|xCounter[3] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~porta_address_reg2 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.059 ; 2.057 ;
; 1.769 ; vga_adapter:VGA|vga_controller:controller|xCounter[3] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a18~porta_address_reg2 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.050 ; 2.053 ;
; 1.775 ; vga_adapter:VGA|vga_controller:controller|yCounter[3] ; vga_adapter:VGA|vga_controller:controller|VGA_VS1 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; -0.002 ; 2.039 ;
; 1.785 ; vga_adapter:VGA|vga_controller:controller|xCounter[3] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a16~porta_address_reg2 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.057 ; 2.076 ;
; 1.793 ; vga_adapter:VGA|vga_controller:controller|xCounter[2] ; vga_adapter:VGA|vga_controller:controller|xCounter[8] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; -0.004 ; 2.055 ;
; 1.803 ; vga_adapter:VGA|vga_controller:controller|xCounter[2] ; vga_adapter:VGA|vga_controller:controller|yCounter[2] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; -0.004 ; 2.065 ;
; 1.808 ; vga_adapter:VGA|vga_controller:controller|xCounter[2] ; vga_adapter:VGA|vga_controller:controller|yCounter[7] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; -0.004 ; 2.070 ;
; 1.809 ; vga_adapter:VGA|vga_controller:controller|xCounter[2] ; vga_adapter:VGA|vga_controller:controller|yCounter[8] ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; -0.004 ; 2.071 ;
; 1.818 ; vga_adapter:VGA|vga_controller:controller|xCounter[1] ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~porta_address_reg0 ; pll|altpll_component|pll|clk[1] ; pll|altpll_component|pll|clk[1] ; 0.000 ; 0.059 ; 2.111 ;
+-------+--------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+---------------------------------+---------------------------------+--------------+------------+------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'CLOCK_50' ;
+-------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
+-------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------------------------------------------------------------------------+
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_address_reg0 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_address_reg0 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_address_reg1 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_address_reg1 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_address_reg10 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_address_reg10 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_address_reg11 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_address_reg11 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_address_reg2 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_address_reg2 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_address_reg3 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_address_reg3 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_address_reg4 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_address_reg4 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_address_reg5 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_address_reg5 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_address_reg6 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_address_reg6 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_address_reg7 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_address_reg7 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_address_reg8 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_address_reg8 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_address_reg9 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_address_reg9 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_datain_reg0 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_datain_reg0 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_memory_reg0 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_memory_reg0 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_we_reg ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~portb_we_reg ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_address_reg0 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_address_reg0 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_address_reg1 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_address_reg1 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_address_reg10 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_address_reg10 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_address_reg11 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_address_reg11 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_address_reg2 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_address_reg2 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_address_reg3 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_address_reg3 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_address_reg4 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_address_reg4 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_address_reg5 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_address_reg5 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_address_reg6 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_address_reg6 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_address_reg7 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_address_reg7 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_address_reg8 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_address_reg8 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_address_reg9 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_address_reg9 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_datain_reg0 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_datain_reg0 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_memory_reg0 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_memory_reg0 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_we_reg ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~portb_we_reg ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_address_reg0 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_address_reg0 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_address_reg1 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_address_reg1 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_address_reg10 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_address_reg10 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_address_reg11 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_address_reg11 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_address_reg2 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_address_reg2 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_address_reg3 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_address_reg3 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_address_reg4 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_address_reg4 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_address_reg5 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_address_reg5 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_address_reg6 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_address_reg6 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_address_reg7 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_address_reg7 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_address_reg8 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_address_reg8 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_address_reg9 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_address_reg9 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_datain_reg0 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_datain_reg0 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_memory_reg0 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_memory_reg0 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_we_reg ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~portb_we_reg ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~portb_address_reg0 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~portb_address_reg0 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~portb_address_reg1 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~portb_address_reg1 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~portb_address_reg10 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~portb_address_reg10 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~portb_address_reg11 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~portb_address_reg11 ;
; 7.620 ; 10.000 ; 2.380 ; High Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~portb_address_reg2 ;
; 7.620 ; 10.000 ; 2.380 ; Low Pulse Width ; CLOCK_50 ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~portb_address_reg2 ;
+-------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------------------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'pll|altpll_component|pll|clk[1]' ;
+--------+--------------+----------------+------------------+---------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
+--------+--------------+----------------+------------------+---------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------+
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~porta_address_reg0 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~porta_address_reg0 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~porta_address_reg1 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~porta_address_reg1 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~porta_address_reg10 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~porta_address_reg10 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~porta_address_reg11 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~porta_address_reg11 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~porta_address_reg2 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~porta_address_reg2 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~porta_address_reg3 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~porta_address_reg3 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~porta_address_reg4 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~porta_address_reg4 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~porta_address_reg5 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~porta_address_reg5 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~porta_address_reg6 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~porta_address_reg6 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~porta_address_reg7 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~porta_address_reg7 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~porta_address_reg8 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~porta_address_reg8 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~porta_address_reg9 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a0~porta_address_reg9 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a1 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a1 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~porta_address_reg0 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~porta_address_reg0 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~porta_address_reg1 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~porta_address_reg1 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~porta_address_reg10 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~porta_address_reg10 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~porta_address_reg11 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~porta_address_reg11 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~porta_address_reg2 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~porta_address_reg2 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~porta_address_reg3 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~porta_address_reg3 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~porta_address_reg4 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~porta_address_reg4 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~porta_address_reg5 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~porta_address_reg5 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~porta_address_reg6 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~porta_address_reg6 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~porta_address_reg7 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~porta_address_reg7 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~porta_address_reg8 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~porta_address_reg8 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~porta_address_reg9 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a10~porta_address_reg9 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~porta_address_reg0 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~porta_address_reg0 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~porta_address_reg1 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~porta_address_reg1 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~porta_address_reg10 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~porta_address_reg10 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~porta_address_reg11 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~porta_address_reg11 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~porta_address_reg2 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~porta_address_reg2 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~porta_address_reg3 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~porta_address_reg3 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~porta_address_reg4 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~porta_address_reg4 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~porta_address_reg5 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~porta_address_reg5 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~porta_address_reg6 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~porta_address_reg6 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~porta_address_reg7 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~porta_address_reg7 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~porta_address_reg8 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~porta_address_reg8 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~porta_address_reg9 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a11~porta_address_reg9 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~porta_address_reg0 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~porta_address_reg0 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~porta_address_reg1 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~porta_address_reg1 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~porta_address_reg10 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~porta_address_reg10 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~porta_address_reg11 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~porta_address_reg11 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~porta_address_reg2 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~porta_address_reg2 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~porta_address_reg3 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~porta_address_reg3 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~porta_address_reg4 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~porta_address_reg4 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~porta_address_reg5 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~porta_address_reg5 ;
; 17.873 ; 20.000 ; 2.127 ; High Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~porta_address_reg6 ;
; 17.873 ; 20.000 ; 2.127 ; Low Pulse Width ; pll|altpll_component|pll|clk[1] ; Rise ; vga_adapter:VGA|altsyncram:VideoMemory|altsyncram_9dg1:auto_generated|altsyncram_97r1:altsyncram1|ram_block2a12~porta_address_reg6 ;
+--------+--------------+----------------+------------------+---------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------+
+----------------------------------------------------------------------------+
; Setup Times ;
+--------------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+--------------+------------+--------+--------+------------+-----------------+
; AUD_ADCDAT ; CLOCK_50 ; 4.626 ; 4.626 ; Rise ; CLOCK_50 ;
; AUD_ADCLRCK ; CLOCK_50 ; 4.508 ; 4.508 ; Rise ; CLOCK_50 ;
; AUD_BCLK ; CLOCK_50 ; 4.646 ; 4.646 ; Rise ; CLOCK_50 ;
; AUD_DACLRCK ; CLOCK_50 ; 4.636 ; 4.636 ; Rise ; CLOCK_50 ;
; DRAM_DQ[*] ; CLOCK_50 ; -1.194 ; -1.194 ; Rise ; CLOCK_50 ;
; DRAM_DQ[0] ; CLOCK_50 ; -1.224 ; -1.224 ; Rise ; CLOCK_50 ;
; DRAM_DQ[1] ; CLOCK_50 ; -1.194 ; -1.194 ; Rise ; CLOCK_50 ;
; DRAM_DQ[2] ; CLOCK_50 ; -1.194 ; -1.194 ; Rise ; CLOCK_50 ;
; DRAM_DQ[3] ; CLOCK_50 ; -1.222 ; -1.222 ; Rise ; CLOCK_50 ;
; DRAM_DQ[4] ; CLOCK_50 ; -1.222 ; -1.222 ; Rise ; CLOCK_50 ;
; DRAM_DQ[5] ; CLOCK_50 ; -1.222 ; -1.222 ; Rise ; CLOCK_50 ;
; DRAM_DQ[6] ; CLOCK_50 ; -1.222 ; -1.222 ; Rise ; CLOCK_50 ;
; DRAM_DQ[7] ; CLOCK_50 ; -1.198 ; -1.198 ; Rise ; CLOCK_50 ;
; DRAM_DQ[8] ; CLOCK_50 ; -1.228 ; -1.228 ; Rise ; CLOCK_50 ;
; DRAM_DQ[9] ; CLOCK_50 ; -1.198 ; -1.198 ; Rise ; CLOCK_50 ;
; DRAM_DQ[10] ; CLOCK_50 ; -1.198 ; -1.198 ; Rise ; CLOCK_50 ;
; DRAM_DQ[11] ; CLOCK_50 ; -1.213 ; -1.213 ; Rise ; CLOCK_50 ;
; DRAM_DQ[12] ; CLOCK_50 ; -1.213 ; -1.213 ; Rise ; CLOCK_50 ;
; DRAM_DQ[13] ; CLOCK_50 ; -1.203 ; -1.203 ; Rise ; CLOCK_50 ;
; DRAM_DQ[14] ; CLOCK_50 ; -1.203 ; -1.203 ; Rise ; CLOCK_50 ;
; DRAM_DQ[15] ; CLOCK_50 ; -1.237 ; -1.237 ; Rise ; CLOCK_50 ;
; KEY[*] ; CLOCK_50 ; 8.188 ; 8.188 ; Rise ; CLOCK_50 ;
; KEY[0] ; CLOCK_50 ; 8.188 ; 8.188 ; Rise ; CLOCK_50 ;
; SW[*] ; CLOCK_50 ; 10.015 ; 10.015 ; Rise ; CLOCK_50 ;
; SW[0] ; CLOCK_50 ; 10.015 ; 10.015 ; Rise ; CLOCK_50 ;
; SW[1] ; CLOCK_50 ; 4.217 ; 4.217 ; Rise ; CLOCK_50 ;
; SW[2] ; CLOCK_50 ; 4.184 ; 4.184 ; Rise ; CLOCK_50 ;
; SW[3] ; CLOCK_50 ; 2.491 ; 2.491 ; Rise ; CLOCK_50 ;
; SW[4] ; CLOCK_50 ; 2.741 ; 2.741 ; Rise ; CLOCK_50 ;
; SW[5] ; CLOCK_50 ; 7.150 ; 7.150 ; Rise ; CLOCK_50 ;
; SW[6] ; CLOCK_50 ; 7.569 ; 7.569 ; Rise ; CLOCK_50 ;
; SW[7] ; CLOCK_50 ; 8.872 ; 8.872 ; Rise ; CLOCK_50 ;
; SW[8] ; CLOCK_50 ; 9.133 ; 9.133 ; Rise ; CLOCK_50 ;
; SW[9] ; CLOCK_50 ; 3.683 ; 3.683 ; Rise ; CLOCK_50 ;
; SW[10] ; CLOCK_50 ; 2.747 ; 2.747 ; Rise ; CLOCK_50 ;
; SW[11] ; CLOCK_50 ; 1.707 ; 1.707 ; Rise ; CLOCK_50 ;
+--------------+------------+--------+--------+------------+-----------------+
+----------------------------------------------------------------------------+
; Hold Times ;
+--------------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+--------------+------------+--------+--------+------------+-----------------+
; AUD_ADCDAT ; CLOCK_50 ; -4.396 ; -4.396 ; Rise ; CLOCK_50 ;
; AUD_ADCLRCK ; CLOCK_50 ; -4.278 ; -4.278 ; Rise ; CLOCK_50 ;
; AUD_BCLK ; CLOCK_50 ; -4.416 ; -4.416 ; Rise ; CLOCK_50 ;
; AUD_DACLRCK ; CLOCK_50 ; -4.406 ; -4.406 ; Rise ; CLOCK_50 ;
; DRAM_DQ[*] ; CLOCK_50 ; 1.401 ; 1.401 ; Rise ; CLOCK_50 ;
; DRAM_DQ[0] ; CLOCK_50 ; 1.388 ; 1.388 ; Rise ; CLOCK_50 ;
; DRAM_DQ[1] ; CLOCK_50 ; 1.358 ; 1.358 ; Rise ; CLOCK_50 ;
; DRAM_DQ[2] ; CLOCK_50 ; 1.358 ; 1.358 ; Rise ; CLOCK_50 ;
; DRAM_DQ[3] ; CLOCK_50 ; 1.386 ; 1.386 ; Rise ; CLOCK_50 ;
; DRAM_DQ[4] ; CLOCK_50 ; 1.386 ; 1.386 ; Rise ; CLOCK_50 ;
; DRAM_DQ[5] ; CLOCK_50 ; 1.386 ; 1.386 ; Rise ; CLOCK_50 ;
; DRAM_DQ[6] ; CLOCK_50 ; 1.386 ; 1.386 ; Rise ; CLOCK_50 ;
; DRAM_DQ[7] ; CLOCK_50 ; 1.362 ; 1.362 ; Rise ; CLOCK_50 ;
; DRAM_DQ[8] ; CLOCK_50 ; 1.392 ; 1.392 ; Rise ; CLOCK_50 ;
; DRAM_DQ[9] ; CLOCK_50 ; 1.362 ; 1.362 ; Rise ; CLOCK_50 ;
; DRAM_DQ[10] ; CLOCK_50 ; 1.362 ; 1.362 ; Rise ; CLOCK_50 ;
; DRAM_DQ[11] ; CLOCK_50 ; 1.377 ; 1.377 ; Rise ; CLOCK_50 ;
; DRAM_DQ[12] ; CLOCK_50 ; 1.377 ; 1.377 ; Rise ; CLOCK_50 ;
; DRAM_DQ[13] ; CLOCK_50 ; 1.367 ; 1.367 ; Rise ; CLOCK_50 ;
; DRAM_DQ[14] ; CLOCK_50 ; 1.367 ; 1.367 ; Rise ; CLOCK_50 ;
; DRAM_DQ[15] ; CLOCK_50 ; 1.401 ; 1.401 ; Rise ; CLOCK_50 ;
; KEY[*] ; CLOCK_50 ; -4.074 ; -4.074 ; Rise ; CLOCK_50 ;
; KEY[0] ; CLOCK_50 ; -4.074 ; -4.074 ; Rise ; CLOCK_50 ;
; SW[*] ; CLOCK_50 ; 0.372 ; 0.372 ; Rise ; CLOCK_50 ;
; SW[0] ; CLOCK_50 ; -2.119 ; -2.119 ; Rise ; CLOCK_50 ;
; SW[1] ; CLOCK_50 ; -0.877 ; -0.877 ; Rise ; CLOCK_50 ;
; SW[2] ; CLOCK_50 ; -1.428 ; -1.428 ; Rise ; CLOCK_50 ;
; SW[3] ; CLOCK_50 ; -0.195 ; -0.195 ; Rise ; CLOCK_50 ;
; SW[4] ; CLOCK_50 ; -0.517 ; -0.517 ; Rise ; CLOCK_50 ;
; SW[5] ; CLOCK_50 ; -2.445 ; -2.445 ; Rise ; CLOCK_50 ;
; SW[6] ; CLOCK_50 ; -2.766 ; -2.766 ; Rise ; CLOCK_50 ;
; SW[7] ; CLOCK_50 ; -4.212 ; -4.212 ; Rise ; CLOCK_50 ;
; SW[8] ; CLOCK_50 ; -4.087 ; -4.087 ; Rise ; CLOCK_50 ;
; SW[9] ; CLOCK_50 ; -0.925 ; -0.925 ; Rise ; CLOCK_50 ;
; SW[10] ; CLOCK_50 ; -0.012 ; -0.012 ; Rise ; CLOCK_50 ;
; SW[11] ; CLOCK_50 ; 0.372 ; 0.372 ; Rise ; CLOCK_50 ;
+--------------+------------+--------+--------+------------+-----------------+
+----------------------------------------------------------------------------------------------+
; Clock to Output Times ;
+----------------+------------+--------+--------+------------+---------------------------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+----------------+------------+--------+--------+------------+---------------------------------+
; AUD_DACDAT ; CLOCK_50 ; 8.395 ; 8.395 ; Rise ; CLOCK_50 ;
; DRAM_ADDR[*] ; CLOCK_50 ; 5.013 ; 5.013 ; Rise ; CLOCK_50 ;
; DRAM_ADDR[0] ; CLOCK_50 ; 4.982 ; 4.982 ; Rise ; CLOCK_50 ;
; DRAM_ADDR[1] ; CLOCK_50 ; 4.992 ; 4.992 ; Rise ; CLOCK_50 ;
; DRAM_ADDR[2] ; CLOCK_50 ; 5.002 ; 5.002 ; Rise ; CLOCK_50 ;
; DRAM_ADDR[3] ; CLOCK_50 ; 5.012 ; 5.012 ; Rise ; CLOCK_50 ;
; DRAM_ADDR[4] ; CLOCK_50 ; 5.012 ; 5.012 ; Rise ; CLOCK_50 ;
; DRAM_ADDR[5] ; CLOCK_50 ; 4.982 ; 4.982 ; Rise ; CLOCK_50 ;
; DRAM_ADDR[6] ; CLOCK_50 ; 4.982 ; 4.982 ; Rise ; CLOCK_50 ;
; DRAM_ADDR[7] ; CLOCK_50 ; 4.983 ; 4.983 ; Rise ; CLOCK_50 ;
; DRAM_ADDR[8] ; CLOCK_50 ; 5.003 ; 5.003 ; Rise ; CLOCK_50 ;
; DRAM_ADDR[9] ; CLOCK_50 ; 5.003 ; 5.003 ; Rise ; CLOCK_50 ;
; DRAM_ADDR[10] ; CLOCK_50 ; 5.013 ; 5.013 ; Rise ; CLOCK_50 ;
; DRAM_ADDR[11] ; CLOCK_50 ; 4.993 ; 4.993 ; Rise ; CLOCK_50 ;
; DRAM_BA_0 ; CLOCK_50 ; 5.070 ; 5.070 ; Rise ; CLOCK_50 ;
; DRAM_BA_1 ; CLOCK_50 ; 5.070 ; 5.070 ; Rise ; CLOCK_50 ;
; DRAM_CAS_N ; CLOCK_50 ; 5.050 ; 5.050 ; Rise ; CLOCK_50 ;
; DRAM_CS_N ; CLOCK_50 ; 5.052 ; 5.052 ; Rise ; CLOCK_50 ;
; DRAM_DQ[*] ; CLOCK_50 ; 5.052 ; 5.052 ; Rise ; CLOCK_50 ;
; DRAM_DQ[0] ; CLOCK_50 ; 4.993 ; 4.993 ; Rise ; CLOCK_50 ;
; DRAM_DQ[1] ; CLOCK_50 ; 5.023 ; 5.023 ; Rise ; CLOCK_50 ;
; DRAM_DQ[2] ; CLOCK_50 ; 5.023 ; 5.023 ; Rise ; CLOCK_50 ;
; DRAM_DQ[3] ; CLOCK_50 ; 5.011 ; 5.011 ; Rise ; CLOCK_50 ;
; DRAM_DQ[4] ; CLOCK_50 ; 5.011 ; 5.011 ; Rise ; CLOCK_50 ;
; DRAM_DQ[5] ; CLOCK_50 ; 5.011 ; 5.011 ; Rise ; CLOCK_50 ;
; DRAM_DQ[6] ; CLOCK_50 ; 5.011 ; 5.011 ; Rise ; CLOCK_50 ;
; DRAM_DQ[7] ; CLOCK_50 ; 5.047 ; 5.047 ; Rise ; CLOCK_50 ;
; DRAM_DQ[8] ; CLOCK_50 ; 5.017 ; 5.017 ; Rise ; CLOCK_50 ;
; DRAM_DQ[9] ; CLOCK_50 ; 5.047 ; 5.047 ; Rise ; CLOCK_50 ;
; DRAM_DQ[10] ; CLOCK_50 ; 5.047 ; 5.047 ; Rise ; CLOCK_50 ;
; DRAM_DQ[11] ; CLOCK_50 ; 5.042 ; 5.042 ; Rise ; CLOCK_50 ;
; DRAM_DQ[12] ; CLOCK_50 ; 5.042 ; 5.042 ; Rise ; CLOCK_50 ;
; DRAM_DQ[13] ; CLOCK_50 ; 5.052 ; 5.052 ; Rise ; CLOCK_50 ;
; DRAM_DQ[14] ; CLOCK_50 ; 5.052 ; 5.052 ; Rise ; CLOCK_50 ;
; DRAM_DQ[15] ; CLOCK_50 ; 5.026 ; 5.026 ; Rise ; CLOCK_50 ;
; DRAM_RAS_N ; CLOCK_50 ; 5.050 ; 5.050 ; Rise ; CLOCK_50 ;
; DRAM_WE_N ; CLOCK_50 ; 5.066 ; 5.066 ; Rise ; CLOCK_50 ;
; HEX2[*] ; CLOCK_50 ; 10.341 ; 10.341 ; Rise ; CLOCK_50 ;
; HEX2[0] ; CLOCK_50 ; 10.266 ; 10.266 ; Rise ; CLOCK_50 ;
; HEX2[1] ; CLOCK_50 ; 10.188 ; 10.188 ; Rise ; CLOCK_50 ;
; HEX2[2] ; CLOCK_50 ; 10.291 ; 10.291 ; Rise ; CLOCK_50 ;
; HEX2[3] ; CLOCK_50 ; 10.341 ; 10.341 ; Rise ; CLOCK_50 ;
; HEX2[4] ; CLOCK_50 ; 10.014 ; 10.014 ; Rise ; CLOCK_50 ;
; HEX2[5] ; CLOCK_50 ; 10.000 ; 10.000 ; Rise ; CLOCK_50 ;
; HEX2[6] ; CLOCK_50 ; 10.023 ; 10.023 ; Rise ; CLOCK_50 ;
; HEX3[*] ; CLOCK_50 ; 10.283 ; 10.283 ; Rise ; CLOCK_50 ;
; HEX3[0] ; CLOCK_50 ; 10.270 ; 10.270 ; Rise ; CLOCK_50 ;
; HEX3[1] ; CLOCK_50 ; 10.080 ; 10.080 ; Rise ; CLOCK_50 ;
; HEX3[2] ; CLOCK_50 ; 10.081 ; 10.081 ; Rise ; CLOCK_50 ;
; HEX3[3] ; CLOCK_50 ; 10.086 ; 10.086 ; Rise ; CLOCK_50 ;
; HEX3[4] ; CLOCK_50 ; 10.049 ; 10.049 ; Rise ; CLOCK_50 ;
; HEX3[5] ; CLOCK_50 ; 10.261 ; 10.261 ; Rise ; CLOCK_50 ;
; HEX3[6] ; CLOCK_50 ; 10.283 ; 10.283 ; Rise ; CLOCK_50 ;
; I2C_SCLK ; CLOCK_50 ; 7.808 ; 7.808 ; Rise ; CLOCK_50 ;
; I2C_SDAT ; CLOCK_50 ; 10.815 ; 10.815 ; Rise ; CLOCK_50 ;
; LEDG[*] ; CLOCK_50 ; 7.434 ; 7.434 ; Rise ; CLOCK_50 ;
; LEDG[8] ; CLOCK_50 ; 7.434 ; 7.434 ; Rise ; CLOCK_50 ;
; LEDR[*] ; CLOCK_50 ; 18.113 ; 18.113 ; Rise ; CLOCK_50 ;
; LEDR[0] ; CLOCK_50 ; 17.289 ; 17.289 ; Rise ; CLOCK_50 ;
; LEDR[1] ; CLOCK_50 ; 15.765 ; 15.765 ; Rise ; CLOCK_50 ;
; LEDR[2] ; CLOCK_50 ; 16.769 ; 16.769 ; Rise ; CLOCK_50 ;
; LEDR[3] ; CLOCK_50 ; 18.113 ; 18.113 ; Rise ; CLOCK_50 ;
; LEDR[4] ; CLOCK_50 ; 15.772 ; 15.772 ; Rise ; CLOCK_50 ;
; LEDR[5] ; CLOCK_50 ; 16.085 ; 16.085 ; Rise ; CLOCK_50 ;
; LEDR[6] ; CLOCK_50 ; 16.821 ; 16.821 ; Rise ; CLOCK_50 ;
; LEDR[7] ; CLOCK_50 ; 16.893 ; 16.893 ; Rise ; CLOCK_50 ;
; LEDR[8] ; CLOCK_50 ; 15.797 ; 15.797 ; Rise ; CLOCK_50 ;
; LEDR[9] ; CLOCK_50 ; 15.355 ; 15.355 ; Rise ; CLOCK_50 ;
; LEDR[10] ; CLOCK_50 ; 15.210 ; 15.210 ; Rise ; CLOCK_50 ;
; LEDR[11] ; CLOCK_50 ; 14.278 ; 14.278 ; Rise ; CLOCK_50 ;
; LEDR[12] ; CLOCK_50 ; 14.127 ; 14.127 ; Rise ; CLOCK_50 ;
; LEDR[13] ; CLOCK_50 ; 14.258 ; 14.258 ; Rise ; CLOCK_50 ;
; LEDR[14] ; CLOCK_50 ; 13.955 ; 13.955 ; Rise ; CLOCK_50 ;
; DRAM_CLK ; CLOCK_50 ; -2.048 ; ; Rise ; pll|altpll_component|pll|clk[0] ;
; DRAM_CLK ; CLOCK_50 ; ; -2.048 ; Fall ; pll|altpll_component|pll|clk[0] ;
; VGA_B[*] ; CLOCK_50 ; 12.220 ; 12.220 ; Rise ; pll|altpll_component|pll|clk[1] ;
; VGA_B[0] ; CLOCK_50 ; 11.921 ; 11.921 ; Rise ; pll|altpll_component|pll|clk[1] ;
; VGA_B[1] ; CLOCK_50 ; 11.921 ; 11.921 ; Rise ; pll|altpll_component|pll|clk[1] ;
; VGA_B[2] ; CLOCK_50 ; 11.915 ; 11.915 ; Rise ; pll|altpll_component|pll|clk[1] ;
; VGA_B[3] ; CLOCK_50 ; 11.905 ; 11.905 ; Rise ; pll|altpll_component|pll|clk[1] ;