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111 | 111 | NEXT_INST |
112 | 112 |
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113 | 113 | #define SS_GET(addr_reg, temp_reg) \ |
114 | | - ldr TEMP4, =65528 SEP \ |
115 | | - cmp addr_reg, TEMP4 SEP \ |
| 114 | + ldr TEMP5, =65528 SEP \ |
| 115 | + cmp addr_reg, TEMP5 SEP \ |
116 | 116 | bhi .exit_shadow_stack_stack_out_of_stack SEP \ |
117 | | - ldr TEMP4, =0 SEP \ |
118 | | - cmp addr_reg, TEMP4 SEP \ |
| 117 | + ldr TEMP5, =0 SEP \ |
| 118 | + cmp addr_reg, TEMP5 SEP \ |
119 | 119 | beq .exit_shadow_stack_stack_out_of_stack SEP \ |
120 | | - add TEMP4, MACHINE, CKB_VM_ASM_ASM_CORE_MACHINE_OFFSET_SHADOW_STACK SEP \ |
121 | | - ldr temp_reg, [TEMP4, addr_reg] |
| 120 | + add TEMP5, MACHINE, CKB_VM_ASM_ASM_CORE_MACHINE_OFFSET_SHADOW_STACK SEP \ |
| 121 | + ldr temp_reg, [TEMP5, addr_reg] |
122 | 122 |
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123 | 123 | #define SS_SET(addr_reg, from_reg) \ |
124 | | - ldr TEMP4, =65528 SEP \ |
125 | | - cmp addr_reg, TEMP4 SEP \ |
| 124 | + ldr TEMP5, =65528 SEP \ |
| 125 | + cmp addr_reg, TEMP5 SEP \ |
126 | 126 | bhi .exit_shadow_stack_stack_out_of_stack SEP \ |
127 | | - ldr TEMP4, =0 SEP \ |
128 | | - cmp addr_reg, TEMP4 SEP \ |
| 127 | + ldr TEMP5, =0 SEP \ |
| 128 | + cmp addr_reg, TEMP5 SEP \ |
129 | 129 | beq .exit_shadow_stack_stack_out_of_stack SEP \ |
130 | | - add TEMP4, MACHINE, CKB_VM_ASM_ASM_CORE_MACHINE_OFFSET_SHADOW_STACK SEP \ |
131 | | - str from_reg, [TEMP4, addr_reg] |
| 130 | + add TEMP5, MACHINE, CKB_VM_ASM_ASM_CORE_MACHINE_OFFSET_SHADOW_STACK SEP \ |
| 131 | + str from_reg, [TEMP5, addr_reg] |
132 | 132 |
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133 | 133 | #define DECODE_R \ |
134 | 134 | ubfx RS1, TEMP1, 0, 8 SEP \ |
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