fix: update nightly version to avoid issue with transitive dependency (#574)

sjudson · web-flow · commit 4dd5ee9e8eb1 · 2026-01-05T14:02:38.000-05:00
* Update nightly version to avoid issue with transitive dependency.

* Update CI.

* Formmating.

* Clippy fix

* Formatting again
diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
@@ -17,7 +17,7 @@ jobs:
         uses: dtolnay/rust-toolchain@stable
         with:
           components: rustfmt
-          toolchain: nightly-2025-04-06
+          toolchain: nightly-2025-05-09
 
       - name: Run `cargo fmt`
         run: |
@@ -41,7 +41,7 @@ jobs:
         uses: dtolnay/rust-toolchain@stable
         with:
           components: clippy
-          toolchain: nightly-2025-04-06
+          toolchain: nightly-2025-05-09
           targets: riscv32im-unknown-none-elf
 
       - name: Add clippy
@@ -79,7 +79,7 @@ jobs:
       - name: Install Rust
         uses: dtolnay/rust-toolchain@stable
         with:
-          toolchain: nightly-2025-04-06
+          toolchain: nightly-2025-05-09
           targets: riscv32im-unknown-none-elf
 
       - name: Install cargo-expand
@@ -113,7 +113,7 @@ jobs:
       - name: Install Rust
         uses: dtolnay/rust-toolchain@stable
         with:
-          toolchain: nightly-2025-04-06 # same version as normal tests
+          toolchain: nightly-2025-05-09 # same version as normal tests
           # need riscv32im-unknown-none-elf for building guest binaries
           targets: wasm32-wasip1, riscv32im-unknown-none-elf
 
@@ -153,7 +153,7 @@ jobs:
       - name: Install Rust
         uses: dtolnay/rust-toolchain@stable
         with:
-          toolchain: nightly-2025-04-06
+          toolchain: nightly-2025-05-09
           targets: riscv32im-unknown-none-elf
 
       - uses: taiki-e/install-action@nextest
@@ -217,7 +217,7 @@ jobs:
       - name: Install Rust
         uses: dtolnay/rust-toolchain@stable
         with:
-          toolchain: nightly-2025-04-06
+          toolchain: nightly-2025-05-09
           targets: riscv32im-unknown-none-elf
 
       - name: Download pre-built host project
diff --git a/cli/src/command/host.rs b/cli/src/command/host.rs
@@ -164,5 +164,5 @@ const GUEST_TEMPLATE_SRC_MAIN: &str = include_str!(concat!(guest_examples_dir!()
 
 // freeze toolchain that works with all provers
 const RUST_TOOLCHAIN: &str = r#"[toolchain]
-channel = "nightly-2025-04-06"
+channel = "nightly-2025-05-09"
 "#;
diff --git a/common/src/memory/alignment.rs b/common/src/memory/alignment.rs
@@ -36,12 +36,7 @@ pub trait Alignable: Sized + Copy + Display + Debug {
     fn is_aligned_to<const N: usize>(self) -> bool;
 
     fn assert_aligned_to<const N: usize>(self) {
-        assert!(
-            self.is_aligned_to::<N>(),
-            "{} is not aligned to {}",
-            self,
-            N
-        );
+        assert!(self.is_aligned_to::<N>(), "{self} is not aligned to {N}");
     }
 
     /// Assert that the value is aligned to a word boundary.
diff --git a/common/src/riscv/instruction.rs b/common/src/riscv/instruction.rs
@@ -72,8 +72,7 @@ impl Instruction {
             // I-type instruction with shamt has 5 bits for shamt.
             debug_assert!(
                 op_c <= 0x1F,
-                "op_c must be in the range [0..32), got {}",
-                op_c
+                "op_c must be in the range [0..32), got {op_c}"
             );
         }
 
@@ -199,7 +198,7 @@ impl Instruction {
         let rd = self.op_a;
         let rs1 = self.op_b;
         let rs2 = Register::from(self.op_c as u8);
-        format!("{} {}, {}, {}", opcode, rd, rs1, rs2)
+        format!("{opcode} {rd}, {rs1}, {rs2}")
     }
 
     fn i_type_to_string(&self, opcode: BuiltinOpcode) -> String {
@@ -210,51 +209,51 @@ impl Instruction {
             BuiltinOpcode::EBREAK | BuiltinOpcode::ECALL => self.opcode.to_string(),
             BuiltinOpcode::JALR => match (rd, rs1, imm12) {
                 (Register::X0, Register::X1, 0) => "ret".to_string(),
-                (Register::X0, _, 0) => format!("jr {}", rs1),
+                (Register::X0, _, 0) => format!("jr {rs1}"),
                 (Register::X1, _, 0) => format!("{} {}", self.opcode, rs1),
-                _ => format!("{} {}, {}, {}", opcode, rd, rs1, imm12),
+                _ => format!("{opcode} {rd}, {rs1}, {imm12}"),
             },
             BuiltinOpcode::ADDI => match (rd, rs1, imm12) {
                 (Register::X0, Register::X0, 0) => "nop".to_string(),
-                (_, Register::X0, _) => format!("li {}, {}", rd, imm12),
-                (_, _, 0) => format!("mv {}, {}", rd, rs1),
-                _ => format!("{} {}, {}, {}", opcode, rd, rs1, imm12),
+                (_, Register::X0, _) => format!("li {rd}, {imm12}"),
+                (_, _, 0) => format!("mv {rd}, {rs1}"),
+                _ => format!("{opcode} {rd}, {rs1}, {imm12}"),
             },
             BuiltinOpcode::LB
             | BuiltinOpcode::LH
             | BuiltinOpcode::LW
             | BuiltinOpcode::LBU
             | BuiltinOpcode::LHU => {
-                format!("{} {}, {}({})", opcode, rd, imm12, rs1)
+                format!("{opcode} {rd}, {imm12}({rs1})")
             }
-            _ => format!("{} {}, {}, {}", opcode, rd, rs1, imm12),
+            _ => format!("{opcode} {rd}, {rs1}, {imm12}"),
         }
     }
 
     fn s_type_to_string(&self, opcode: BuiltinOpcode) -> String {
         let rs1 = self.op_a;
         let rs2 = self.op_b;
         let imm12 = self.op_c as i32;
-        format!("{} {}, {}({})", opcode, rs2, imm12, rs1)
+        format!("{opcode} {rs2}, {imm12}({rs1})")
     }
 
     fn b_type_to_string(&self, opcode: BuiltinOpcode) -> String {
         let rs1 = self.op_a;
         let rs2 = self.op_b;
         let imm12 = self.op_c as i32;
-        format!("{} {}, {}, 0x{:x}", opcode, rs1, rs2, imm12)
+        format!("{opcode} {rs1}, {rs2}, 0x{imm12:x}")
     }
 
     fn u_type_to_string(&self, opcode: BuiltinOpcode) -> String {
         let rd = self.op_a;
         let imm20 = self.op_c;
-        format!("{} {}, 0x{:x}", opcode, rd, imm20)
+        format!("{opcode} {rd}, 0x{imm20:x}")
     }
 
     fn j_type_to_string(&self, opcode: BuiltinOpcode) -> String {
         let rd = self.op_a;
         let imm20 = self.op_c as i32;
-        format!("{} {}, 0x{:x}", opcode, rd, imm20)
+        format!("{opcode} {rd}, 0x{imm20:x}")
     }
 
     // Encode the instruction struct to binary representation.
diff --git a/common/src/riscv/register.rs b/common/src/riscv/register.rs
@@ -188,8 +188,7 @@ mod tests {
             assert_eq!(
                 reg.abi_name(),
                 abi_names[i as usize],
-                "Mismatch for register X{}",
-                i
+                "Mismatch for register X{i}"
             );
         }
     }
@@ -199,7 +198,7 @@ mod tests {
         for i in 0..32 {
             let reg = Register::from(i);
             assert_eq!(
-                format!("{}", reg),
+                format!("{reg}"),
                 reg.abi_name(),
                 "Display mismatch for register X{}",
                 i
diff --git a/prover/src/chips/instructions/i/syscall.rs b/prover/src/chips/instructions/i/syscall.rs
@@ -71,8 +71,7 @@ impl MachineChip for SyscallChip {
             (0x405, None) => traces.fill_columns(row_idx, true, Column::IsSysMemoryAdvise),
             _ => {
                 panic!(
-                    "Unknown syscall number: 0x{:x} and result: {:?}, on row {}",
-                    syscall_number, result, row_idx
+                    "Unknown syscall number: 0x{syscall_number:x} and result: {result:?}, on row {row_idx}"
                 );
             }
         };
diff --git a/prover/src/chips/instructions/m/nexani.rs b/prover/src/chips/instructions/m/nexani.rs
@@ -173,7 +173,7 @@ pub(super) fn mull_limb(b: u32, c: u32) -> MulResult {
     let (a23, carry_1) = (a23 as u16, (a23 >> 16));
 
     // Verify our calculations match the built-in multiplication
-    assert!(carry_1 < 5, "Carry_1 exceeds expected bounds {}", carry_1);
+    assert!(carry_1 < 5, "Carry_1 exceeds expected bounds {carry_1}");
     assert_eq!(
         a01.to_le_bytes(),
         [a_l_bytes[0], a_l_bytes[1]],
@@ -217,7 +217,7 @@ pub(super) fn mull_limb(b: u32, c: u32) -> MulResult {
         .wrapping_add((c3_prime_prime) << 8);
     let (a45, carry_2) = (a45 as u16, (a45 >> 16));
 
-    assert!(carry_2 < 4, "Carry_2 exceeds expected bounds {}", carry_2);
+    assert!(carry_2 < 4, "Carry_2 exceeds expected bounds {carry_2}");
 
     // Bytes 6-7 of the final result
     let a67 = (z3 as u32)
diff --git a/prover/src/chips/memory_check/register_mem_check.rs b/prover/src/chips/memory_check/register_mem_check.rs
@@ -412,10 +412,7 @@ fn fill_prev_values(
     let cur_value = u32::from_base_fields(reg_value);
     assert!(
         reg_idx != 0 || cur_value == 0,
-        "writing non-zero to X0, reg_idx: {}, cur_value: {}, row_idx: {}",
-        reg_idx,
-        cur_value,
-        row_idx
+        "writing non-zero to X0, reg_idx: {reg_idx}, cur_value: {cur_value}, row_idx: {row_idx}"
     );
     let AccessResult {
         prev_timestamp,
diff --git a/prover/src/chips/range_check/range128.rs b/prover/src/chips/range_check/range128.rs
@@ -189,7 +189,7 @@ fn fill_main_col(value_col: BaseField, selector_col: BaseField, side_note: &mut
     }
     let checked = value_col.0;
     #[cfg(not(test))] // Tests need to go past this assertion and break constraints.
-    assert!(checked < 128, "value is out of range {}", checked);
+    assert!(checked < 128, "value is out of range {checked}");
     side_note.range128.multiplicity[checked as usize] += 1;
 }
 
diff --git a/prover/src/chips/range_check/range16.rs b/prover/src/chips/range_check/range16.rs
@@ -272,10 +272,7 @@ fn fill_main_for_type<VC: VirtualColumn<1>>(
             let [is_type] = VC::read_from_traces_builder(traces, row_idx);
             !is_type.is_zero()
         },
-        "ProgramStep and the TraceBuilder seem to disagree which type of instruction is being processed at row {}; step: {:?}, instruction_type: {:?}",
-        row_idx,
-        step,
-        instruction_type,
+        "ProgramStep and the TraceBuilder seem to disagree which type of instruction is being processed at row {row_idx}; step: {step:?}, instruction_type: {instruction_type:?}",
     );
     if step_is_of_type {
         for col in columns.iter() {
@@ -288,7 +285,7 @@ fn fill_main_for_type<VC: VirtualColumn<1>>(
 fn fill_main_elm(col: BaseField, side_note: &mut SideNote) {
     let checked = col.0;
     #[cfg(not(test))] // Tests need to go past this assertion and break constraints.
-    assert!(checked < 16, "value is out of range {}", checked);
+    assert!(checked < 16, "value is out of range {checked}");
     side_note.range16.multiplicity[checked as usize] += 1;
 }
 
diff --git a/prover/src/chips/range_check/range256.rs b/prover/src/chips/range_check/range256.rs
@@ -263,7 +263,7 @@ fn fill_main_cols<const N: usize>(value_col: [BaseField; N], side_note: &mut Sid
     for (_limb_index, limb) in value_col.iter().enumerate() {
         let checked = limb.0;
         #[cfg(not(test))] // Tests need to go past this assertion and break constraints.
-        assert!(checked < 256, "value[{}] is out of range", _limb_index);
+        assert!(checked < 256, "value[{_limb_index}] is out of range");
         side_note.range256.multiplicity[checked as usize] += 1;
     }
 }
diff --git a/prover/src/chips/range_check/range32.rs b/prover/src/chips/range_check/range32.rs
@@ -105,7 +105,7 @@ impl MachineChip for Range32Chip {
 fn fill_main_elm(col: BaseField, side_note: &mut SideNote) {
     let checked = col.0;
     #[cfg(not(test))] // Tests need to go past this assertion and break constraints.
-    assert!(checked < 32, "value is out of range {}", checked);
+    assert!(checked < 32, "value is out of range {checked}");
     side_note.range32.multiplicity[checked as usize] += 1;
 }
 
diff --git a/prover/src/chips/range_check/range8.rs b/prover/src/chips/range_check/range8.rs
@@ -281,10 +281,7 @@ fn fill_main_for_type<VC: VirtualColumn<1>>(
             let [is_type] = VC::read_from_traces_builder(traces, row_idx);
             !is_type.is_zero()
         },
-        "ProgramStep and the TraceBuilder seem to disagree which type of instruction is being processed at row {}; step: {:?}, instruction_type: {:?}",
-        row_idx,
-        step,
-        instruction_type,
+        "ProgramStep and the TraceBuilder seem to disagree which type of instruction is being processed at row {row_idx}; step: {step:?}, instruction_type: {instruction_type:?}",
     );
     if step_is_of_type {
         for col in columns.iter() {
@@ -297,6 +294,6 @@ fn fill_main_for_type<VC: VirtualColumn<1>>(
 fn fill_main_elm(col: BaseField, side_note: &mut SideNote) {
     let checked = col.0;
     #[cfg(not(test))] // Tests need to go past this assertion and break constraints.
-    assert!(checked < 8, "value is out of range {}", checked);
+    assert!(checked < 8, "value is out of range {checked}");
     side_note.range8.multiplicity[checked as usize] += 1;
 }
diff --git a/prover/src/extensions/multiplicity.rs b/prover/src/extensions/multiplicity.rs
@@ -95,7 +95,7 @@ impl<const LEN: usize> RangeValues<LEN> {
 
     pub fn id(&self) -> PreProcessedColumnId {
         PreProcessedColumnId {
-            id: format!("preprocessed_range_values_{}", LEN),
+            id: format!("preprocessed_range_values_{LEN}"),
         }
     }
 }
diff --git a/prover/src/extensions/ram_init_final.rs b/prover/src/extensions/ram_init_final.rs
@@ -62,7 +62,7 @@ impl FrameworkEval for RamInitFinalEval {
         // Retrieve all preprocessed columns in the same order as generated
         let preprocessed_ram_addr: Vec<E::F> = (0..WORD_SIZE)
             .map(|i| {
-                let col_id = format!("preprocessed_ram_init_final_addr{}", i);
+                let col_id = format!("preprocessed_ram_init_final_addr{i}");
                 eval.get_preprocessed_column(PreProcessedColumnId { id: col_id })
             })
             .collect();
@@ -504,7 +504,7 @@ impl RamInitFinal {
             ret.push(base_column);
         });
         ret.iter().enumerate().for_each(|(i, col)| {
-            assert_eq!(col.length, num_rows, "{}th element has wrong length", i);
+            assert_eq!(col.length, num_rows, "{i}th element has wrong length");
         });
         assert!(ret.len() == 2 * WORD_SIZE + 2);
         ret
@@ -657,9 +657,7 @@ impl RamInitFinal {
             #[cfg(not(test))]
             assert!(
                 checked < 256,
-                "final value {} out of range at index {}",
-                checked,
-                _i
+                "final value {checked} out of range at index {_i}"
             );
             side_note.range256.multiplicity[checked as usize] += 1;
         }
diff --git a/runtime/build.rs b/runtime/build.rs
@@ -8,7 +8,7 @@ fn main() {
 
     let linker_script_path = "./linker-scripts/default.x";
     let linker_script_bytes = fs::read(linker_script_path).unwrap();
-    println!("cargo:rerun-if-changed={}", linker_script_path);
+    println!("cargo:rerun-if-changed={linker_script_path}");
 
     let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap());
     fs::write(out_dir.join("link.x"), linker_script_bytes).unwrap();
diff --git a/rust-toolchain.toml b/rust-toolchain.toml
@@ -1,2 +1,2 @@
 [toolchain]
-channel = "nightly-2025-04-06"
+channel = "nightly-2025-05-09"
diff --git a/sdk/README.md b/sdk/README.md
@@ -17,13 +17,13 @@ $ rustup target add riscv32im-unknown-none-elf
 Then, install the Nexus zkVM:
 
 ```shell
-$ rustup run nightly-2025-04-06 cargo install --git https://github.com/nexus-xyz/nexus-zkvm cargo-nexus --tag 'v0.3.5'
+$ rustup run nightly-2025-05-09 cargo install --git https://github.com/nexus-xyz/nexus-zkvm cargo-nexus --tag 'v0.3.5'
 ```
 
 And verify the installation:
 
 ```shell
-$ rustup run nightly-2025-04-06 cargo nexus --help
+$ rustup run nightly-2025-05-09 cargo nexus --help
 ```
 
 This should print the available CLI commands. At present, the `cargo nexus` CLI is minimal, providing just a `cargo nexus host` command to setup an SDK based project.
@@ -33,7 +33,7 @@ This should print the available CLI commands. At present, the `cargo nexus` CLI
 To use the zkVM programmatically, we need two programs: a _guest_ program that runs on the zkVM, and a _host_ program that operates the zkVM itself. Run:
 
 ```shell
-$ rustup run nightly-2025-04-06 cargo nexus host nexus-host
+$ rustup run nightly-2025-05-09 cargo nexus host nexus-host
 ```
 
 This will create a new Rust project directory with the following structure:
diff --git a/vm/build.rs b/vm/build.rs
@@ -66,9 +66,9 @@ fn main() {
     let two_precompiles_path = built_bin_dir.join(TWO_PRECOMPILES_NAME);
     let no_precompiles_path = built_bin_dir.join(NO_PRECOMPILES_NAME);
 
-    let one_precompile_dest = test_dir.join(format!("{}.elf", ONE_PRECOMPILE_NAME));
-    let two_precompiles_dest = test_dir.join(format!("{}.elf", TWO_PRECOMPILES_NAME));
-    let no_precompiles_dest = test_dir.join(format!("{}.elf", NO_PRECOMPILES_NAME));
+    let one_precompile_dest = test_dir.join(format!("{ONE_PRECOMPILE_NAME}.elf"));
+    let two_precompiles_dest = test_dir.join(format!("{TWO_PRECOMPILES_NAME}.elf"));
+    let no_precompiles_dest = test_dir.join(format!("{NO_PRECOMPILES_NAME}.elf"));
 
     std::fs::copy(one_precompile_path, one_precompile_dest).unwrap();
     std::fs::copy(two_precompiles_path, two_precompiles_dest).unwrap();
diff --git a/vm/src/elf/loader.rs b/vm/src/elf/loader.rs
diff --git a/vm/src/elf/parser.rs b/vm/src/elf/parser.rs
diff --git a/vm/src/memory/unified.rs b/vm/src/memory/unified.rs
diff --git a/vm/src/memory/variable.rs b/vm/src/memory/variable.rs
diff --git a/vm/src/riscv/instructions/basic_block.rs b/vm/src/riscv/instructions/basic_block.rs

Original file line number	Diff line number	Diff line change
`@@ -188,8 +188,7 @@ mod tests {`
`188`	`188`	`assert_eq!(`
`189`	`189`	`reg.abi_name(),`
`190`	`190`	`abi_names[i as usize],`
`191`		`- "Mismatch for register X{}",`
`192`		`- i`
	`191`	`+ "Mismatch for register X{i}"`
`193`	`192`	`);`
`194`	`193`	`}`
`195`	`194`	`}`
`@@ -199,7 +198,7 @@ mod tests {`
`199`	`198`	`for i in 0..32 {`
`200`	`199`	`let reg = Register::from(i);`
`201`	`200`	`assert_eq!(`
`202`		`- format!("{}", reg),`
	`201`	`+ format!("{reg}"),`
`203`	`202`	`reg.abi_name(),`
`204`	`203`	`"Display mismatch for register X{}",`
`205`	`204`	`i`
Original file line number	Diff line number	Diff line change
`@@ -189,7 +189,7 @@ fn fill_main_col(value_col: BaseField, selector_col: BaseField, side_note: &mut`
`189`	`189`	`}`
`190`	`190`	`let checked = value_col.0;`
`191`	`191`	`#[cfg(not(test))] // Tests need to go past this assertion and break constraints.`
`192`		`- assert!(checked < 128, "value is out of range {}", checked);`
	`192`	`+ assert!(checked < 128, "value is out of range {checked}");`
`193`	`193`	`side_note.range128.multiplicity[checked as usize] += 1;`
`194`	`194`	`}`
`195`	`195`