Port Getting Started - External Memory.lvproj to PXIe-6593 #12
Description
The Getting Started - External Memory.lvproj demonstrates how to access external DRAM memory from the FPGA. Demonstrated access methods include Low Level memory primitives, Memory IDL, and DRAM FIFO.
It is written for the PXIe-7976. This issue is to port this example to the PXIe-6593.