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Description
Description
When assigning an others value to an unconstrained std_logic_vector
the compiler throws an error. By using the --relaxed
option this error should be suppressed.
With GHDL this error is suppressed by using -frelaxed
.
How to reproduce?
In the following a minimal working example to reproduce
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity module is
port (
vec : out std_logic_vector
);
end entity;
architecture rtl of module is
begin
vec <= (others => '1');
end architecture;
The following commands have been used for execution:
nvc --std=08 -a --relaxed test_unconstrained_others.vhdl # NVC
ghdl -a --std=08 -frelaxed test_unconstrained_others.vhdl # GHDL
Context
- OS: Windows + MSYS2/UCRT64
- Origin:
- Built from sources:
nvc 1.15.2 (1.15.2.r0.g2fe12d4f)
- Built from sources:
/cc @Paebbels