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Add core performance for 4-level tiling pipeline #2655

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Add core performance for 4-level tiling pipeline

Add core performance for 4-level tiling pipeline #2655

Triggered via pull request March 11, 2025 22:44
@newlingnewling
synchronize #1177
newling:four_level_core_perf_bench
Status Success
Total duration 1h 27m 28s
Artifacts 2

ci-windows.yml

on: pull_request
Build and Test (windows, ASSERTIONS)
14m 43s
Build and Test (windows, ASSERTIONS)
E2E Test windows
1h 12m
E2E Test windows
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2 warnings
Build and Test (windows, ASSERTIONS): compiler/plugins/target/AMD-AIE/aievec/AIEVecTypeConstraints.td#L69
unused template argument: isOperandResultTypePairValidForAIE2MulElem:rhs
Build and Test (windows, ASSERTIONS): compiler/plugins/target/AMD-AIE/aievec/AIEVecTypeConstraints.td#L69
unused template argument: isOperandResultTypePairValidForAIE2MulElem:rhs

Artifacts

Produced during runtime
Name Size Digest
windows_x86_64_iree_packages Expired
404 MB
sha256:f5dfa968df501a5b1a241d6417cf31c73bea00a7c998d1da4130e186262482cd
windows_x86_64_llvm_packages Expired
705 MB
sha256:caa5f857db8b044bc69504876e2b74dec97c458b161a517ba52e715cb8823464