Skip to content

Commit 13d6fed

Browse files
PizzaAllTheWayPizzaAllTheWay
committed
samples: peripherals: spi_mngr: add SPI manager NOR flash sample
Add a non-blocking sample that exercises read, page program, and sector erase on the on-board external NOR flash through the SPI manager library. Buttons trigger the operations and the read result is logged as a hex dump. Wire up BOARD_EXTERNAL_MEMORY_* macros (SPIM instance, SCK/MOSI/MISO/CS and WP#/RST# strap pins) in the affected board-config.h files so the sample picks up the on-board flash automatically. Signed-off-by: Martynas Smilingis <martynas.smilingis@nordicsemi.no>
1 parent a83db65 commit 13d6fed

11 files changed

Lines changed: 536 additions & 2 deletions

File tree

‎boards/nordic/bm_nrf54l15dk/include/board-config.h‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,30 @@ extern "C" {
6363
#define BOARD_CONSOLE_UARTE_PIN_CTS NRF_PIN_PORT_TO_PIN_NUMBER(7, 1)
6464
#endif
6565

66+
/* External SPI memory pins. */
67+
#ifndef BOARD_EXTERNAL_MEMORY_SPIM_INST
68+
#define BOARD_EXTERNAL_MEMORY_SPIM_INST NRF_SPIM00
69+
#endif
70+
71+
#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_SCK
72+
#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_SCK NRF_PIN_PORT_TO_PIN_NUMBER(1, 2)
73+
#endif
74+
#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_MOSI
75+
#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_MOSI NRF_PIN_PORT_TO_PIN_NUMBER(2, 2)
76+
#endif
77+
#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_MISO
78+
#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_MISO NRF_PIN_PORT_TO_PIN_NUMBER(4, 2)
79+
#endif
80+
#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_CSN
81+
#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_CSN NRF_PIN_PORT_TO_PIN_NUMBER(5, 2)
82+
#endif
83+
#ifndef BOARD_EXTERNAL_MEMORY_PIN_WP
84+
#define BOARD_EXTERNAL_MEMORY_PIN_WP NRF_PIN_PORT_TO_PIN_NUMBER(3, 2)
85+
#endif
86+
#ifndef BOARD_EXTERNAL_MEMORY_PIN_RST
87+
#define BOARD_EXTERNAL_MEMORY_PIN_RST NRF_PIN_PORT_TO_PIN_NUMBER(0, 2)
88+
#endif
89+
6690
/* Application UART configuration */
6791
#ifndef BOARD_APP_UARTE_INST
6892
#define BOARD_APP_UARTE_INST NRF_UARTE30

‎boards/nordic/bm_nrf54lm20dk/include/board-config.h‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,30 @@ extern "C" {
6363
#define BOARD_CONSOLE_UARTE_PIN_CTS NRF_PIN_PORT_TO_PIN_NUMBER(19, 1)
6464
#endif
6565

66+
/* External SPI memory pins. */
67+
#ifndef BOARD_EXTERNAL_MEMORY_SPIM_INST
68+
#define BOARD_EXTERNAL_MEMORY_SPIM_INST NRF_SPIM00
69+
#endif
70+
71+
#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_SCK
72+
#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_SCK NRF_PIN_PORT_TO_PIN_NUMBER(1, 2)
73+
#endif
74+
#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_MOSI
75+
#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_MOSI NRF_PIN_PORT_TO_PIN_NUMBER(2, 2)
76+
#endif
77+
#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_MISO
78+
#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_MISO NRF_PIN_PORT_TO_PIN_NUMBER(4, 2)
79+
#endif
80+
#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_CSN
81+
#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_CSN NRF_PIN_PORT_TO_PIN_NUMBER(5, 2)
82+
#endif
83+
#ifndef BOARD_EXTERNAL_MEMORY_PIN_WP
84+
#define BOARD_EXTERNAL_MEMORY_PIN_WP NRF_PIN_PORT_TO_PIN_NUMBER(3, 2)
85+
#endif
86+
#ifndef BOARD_EXTERNAL_MEMORY_PIN_RST
87+
#define BOARD_EXTERNAL_MEMORY_PIN_RST NRF_PIN_PORT_TO_PIN_NUMBER(0, 2)
88+
#endif
89+
6690
/* Application UART configuration */
6791
#ifndef BOARD_APP_UARTE_INST
6892
#define BOARD_APP_UARTE_INST NRF_UARTE30

‎boards/nordic/bm_nrf54ls05dk/include/board-config.h‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,30 @@ extern "C" {
6363
#define BOARD_CONSOLE_UARTE_PIN_CTS NRF_PIN_PORT_TO_PIN_NUMBER(7, 1)
6464
#endif
6565

66+
/* External SPI memory pins. */
67+
#ifndef BOARD_EXTERNAL_MEMORY_SPIM_INST
68+
#define BOARD_EXTERNAL_MEMORY_SPIM_INST NRF_SPIM21
69+
#endif
70+
71+
#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_SCK
72+
#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_SCK NRF_PIN_PORT_TO_PIN_NUMBER(2, 1)
73+
#endif
74+
#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_MOSI
75+
#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_MOSI NRF_PIN_PORT_TO_PIN_NUMBER(3, 1)
76+
#endif
77+
#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_MISO
78+
#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_MISO NRF_PIN_PORT_TO_PIN_NUMBER(5, 1)
79+
#endif
80+
#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_CSN
81+
#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_CSN NRF_PIN_PORT_TO_PIN_NUMBER(6, 1)
82+
#endif
83+
#ifndef BOARD_EXTERNAL_MEMORY_PIN_WP
84+
#define BOARD_EXTERNAL_MEMORY_PIN_WP NRF_PIN_PORT_TO_PIN_NUMBER(0, 1)
85+
#endif
86+
#ifndef BOARD_EXTERNAL_MEMORY_PIN_RST
87+
#define BOARD_EXTERNAL_MEMORY_PIN_RST NRF_PIN_PORT_TO_PIN_NUMBER(1, 1)
88+
#endif
89+
6690
/* Application UART configuration */
6791
#ifndef BOARD_APP_UARTE_INST
6892
#define BOARD_APP_UARTE_INST NRF_UARTE21

‎boards/nordic/bm_nrf54lv10dk/include/board-config.h‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,30 @@ extern "C" {
6363
#define BOARD_CONSOLE_UARTE_PIN_CTS NRF_PIN_PORT_TO_PIN_NUMBER(7, 1)
6464
#endif
6565

66+
/* External SPI memory pins. */
67+
#ifndef BOARD_EXTERNAL_MEMORY_SPIM_INST
68+
#define BOARD_EXTERNAL_MEMORY_SPIM_INST NRF_SPIM21
69+
#endif
70+
71+
#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_SCK
72+
#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_SCK NRF_PIN_PORT_TO_PIN_NUMBER(0, 1)
73+
#endif
74+
#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_MOSI
75+
#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_MOSI NRF_PIN_PORT_TO_PIN_NUMBER(1, 1)
76+
#endif
77+
#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_MISO
78+
#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_MISO NRF_PIN_PORT_TO_PIN_NUMBER(2, 1)
79+
#endif
80+
#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_CSN
81+
#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_CSN NRF_PIN_PORT_TO_PIN_NUMBER(3, 1)
82+
#endif
83+
#ifndef BOARD_EXTERNAL_MEMORY_PIN_WP
84+
#define BOARD_EXTERNAL_MEMORY_PIN_WP NRF_PIN_PORT_TO_PIN_NUMBER(5, 0)
85+
#endif
86+
#ifndef BOARD_EXTERNAL_MEMORY_PIN_RST
87+
#define BOARD_EXTERNAL_MEMORY_PIN_RST NRF_PIN_PORT_TO_PIN_NUMBER(6, 0)
88+
#endif
89+
6690
/* Application UART configuration */
6791
#ifndef BOARD_APP_UARTE_INST
6892
#define BOARD_APP_UARTE_INST NRF_UARTE30

‎doc/nrf-bm/release_notes/release_notes_changelog.rst‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,4 @@
1+
```rst
12
.. _nrf_bm_release_notes_2099:
23
34
Changelog for |BMlong| v2.0.99
@@ -33,7 +34,7 @@ No changes since the latest nRF Connect SDK Bare Metal release.
3334
Boards
3435
======
3536
36-
No changes since the latest nRF Connect SDK Bare Metal release.
37+
* Added ``BOARD_EXTERNAL_MEMORY_*`` macros to the affected ``board-config.h`` files (SPIM instance, SCK/MOSI/MISO/CS and WP#/RST# strap pins) so samples can target the on-board external NOR flash without hardcoding pins.
3738

3839
Build system
3940
============
@@ -120,7 +121,7 @@ No changes since the latest nRF Connect SDK Bare Metal release.
120121
Peripheral samples
121122
------------------
122123

123-
No changes since the latest nRF Connect SDK Bare Metal release.
124+
* Added the :ref:`spi_mngr_sample` sample, demonstrating non-blocking read, page program, and sector erase on the on-board external NOR flash using the :ref:`lib_bm_spi_mngr` library.
124125

125126
DFU samples
126127
-----------
@@ -141,3 +142,4 @@ Documentation
141142
=============
142143

143144
No changes since the latest nRF Connect SDK Bare Metal release.
145+
```

‎samples/peripherals/spi_mngr/CMakeLists.txt‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
#
2+
# Copyright (c) 2026 Nordic Semiconductor ASA
3+
#
4+
# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
5+
#
6+
7+
cmake_minimum_required(VERSION 3.20.0)
8+
9+
find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
10+
project(spi_mngr)
11+
12+
target_sources(app PRIVATE src/main.c)

‎samples/peripherals/spi_mngr/Kconfig‎

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,22 @@
1+
#
2+
# Copyright (c) 2026 Nordic Semiconductor ASA
3+
#
4+
# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
5+
#
6+
7+
menu "SPI Manager sample"
8+
9+
config SAMPLE_SPI_MNGR_MSG
10+
string "Message to write to external NOR flash"
11+
default "Hello World!"
12+
help
13+
Payload bytes written to the external NOR flash when a program operation is triggered.
14+
Truncated to 64 bytes if longer.
15+
16+
module=SAMPLE_SPI_MNGR
17+
module-str=SPI manager sample
18+
source "$(ZEPHYR_BASE)/subsys/logging/Kconfig.template.log_config"
19+
20+
endmenu # "SPI Manager sample"
21+
22+
source "Kconfig.zephyr"

‎samples/peripherals/spi_mngr/README.rst‎

Lines changed: 89 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,89 @@
1+
.. _spi_mngr_sample:
2+
3+
SPI manager: external NOR flash
4+
###############################
5+
6+
.. contents::
7+
:local:
8+
:depth: 2
9+
10+
The SPI manager sample demonstrates how to use the :ref:`lib_bm_spi_mngr` library with |BMlong| to perform non-blocking read, page program, and sector erase operations on the external flash memory of the development kit.
11+
12+
Requirements
13+
************
14+
15+
The sample supports the following development kits:
16+
17+
.. tabs::
18+
19+
.. group-tab:: Simple board variants
20+
21+
The following board variants do **not** have DFU capabilities:
22+
23+
.. include:: /includes/supported_boards_all_non-mcuboot_variants_s115.txt
24+
25+
.. include:: /includes/supported_boards_all_non-mcuboot_variants_s145.txt
26+
27+
.. group-tab:: MCUboot board variants
28+
29+
The following board variants have DFU capabilities:
30+
31+
.. include:: /includes/supported_boards_all_mcuboot_variants_s115.txt
32+
33+
.. include:: /includes/supported_boards_all_mcuboot_variants_s145.txt
34+
35+
.. important::
36+
You must enable the external flash on the development kit before flashing the sample. To do so, open **nRF Connect for Desktop**, go to **Board Configurator**, enable **external storage**, and write the configuration to the board. Without this step, the on-board flash is neither powered nor routed to the SoC, and the sample does not work.
37+
38+
Overview
39+
********
40+
41+
The sample uses the SPI manager library to schedule read, program, and erase operations on the external flash without blocking the CPU. All operations target the same flash address (``FLASH_ADDR`` in :file:`main.c`) and share a single SPI manager instance.
42+
43+
The flash is the on-board MX25-class NOR device on the development kit. Its SPI and strap pins are defined by the ``BOARD_EXTERNAL_MEMORY_*`` macros in :file:`board-config.h`.
44+
45+
User interface
46+
**************
47+
48+
LED 0:
49+
Lit when the device is initialized.
50+
51+
Button 1:
52+
Erase the flash sector.
53+
54+
Button 2:
55+
Read from the flash and log the data as a hex dump.
56+
57+
Button 3:
58+
Program the message defined by :kconfig:option:`CONFIG_SAMPLE_SPI_MNGR_MSG` to the flash.
59+
60+
Configuration
61+
*************
62+
63+
Set the message written to flash through the following Kconfig option:
64+
65+
* :kconfig:option:`CONFIG_SAMPLE_SPI_MNGR_MSG`. String written to the external flash during a program operation. The string is truncated to 64 bytes if longer. The default value is ``"Hello World!"``.
66+
67+
Building and running
68+
********************
69+
70+
This sample can be found under :file:`samples/peripherals/spi_mngr/` in the |BMshort| folder structure.
71+
72+
For details on how to create, configure, and program a sample, see :ref:`getting_started_with_the_samples`.
73+
74+
Testing
75+
=======
76+
77+
Make sure that you have enabled **external storage** in the Board Configurator (see the note in the Requirements section) before flashing the sample.
78+
79+
You can then test the sample by performing the following steps:
80+
81+
1. Compile and program the application.
82+
#. Open a serial terminal and observe the startup log, which lists the buttons and their operations.
83+
#. Press **Button 2** to read the on-board flash. The hex dump shows either all ``0xFF`` (erased) or whatever was last written to the address in a previous session.
84+
#. Press **Button 3** to program the configured message. The log prints ``Programming "Hello World!" @ 0x00100000``.
85+
#. Press **Button 2** again. The hex dump now starts with the message bytes, confirming that the write succeeded. For the default configuration, this is ``48 65 6c 6c 6f 20 57 6f 72 6c 64 21`` followed by ``0xFF`` padding.
86+
#. Power-cycle the board and press **Button 2** without programming again. The same message reappears, which confirms that the data is non-volatile and persists in the external flash across resets.
87+
#. Press **Button 1** to erase the sector. Wait a moment for the chip to finish the self-timed erase.
88+
#. Power-cycle the board and press **Button 2**. The hex dump shows all ``0xFF`` again, which confirms that the erase removed the data.
89+
#. Optionally, change :kconfig:option:`CONFIG_SAMPLE_SPI_MNGR_MSG` to a different string, rebuild, and repeat steps 4 to 6 to verify that your custom message is written and persists across reboots.

‎samples/peripherals/spi_mngr/prj.conf‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
# Logging
2+
CONFIG_LOG=y
3+
CONFIG_LOG_BACKEND_BM_UARTE=y
4+
5+
# Enabling SoftDevice is not strictly needed, though we are building with SoftDevice boards.
6+
CONFIG_SOFTDEVICE=y
7+
8+
# Buttons, LEDs ans timer
9+
CONFIG_BM_BUTTONS=y
10+
CONFIG_BM_GPIOTE=y
11+
CONFIG_BM_TIMER=y
12+
13+
# HFCLK and related clock services for SoC peripherals.
14+
CONFIG_CLOCK_CONTROL=y
15+
16+
# SPIM hardware driver, required by bm_spi_mngr for SPI master transfers.
17+
CONFIG_NRFX_SPIM=y
18+
# Queued SPI transactions on top of nrfx SPIM.
19+
CONFIG_BM_SPI_MNGR=y

‎samples/peripherals/spi_mngr/sample.yaml‎

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,34 @@
1+
sample:
2+
name: SPI Manager Sample
3+
tests:
4+
sample.spi_mngr:
5+
sysbuild: true
6+
build_only: true
7+
integration_platforms:
8+
- bm_nrf54l15dk/nrf54l15/cpuapp/s115_softdevice
9+
platform_allow:
10+
- bm_nrf54l15dk/nrf54l05/cpuapp/s115_softdevice
11+
- bm_nrf54l15dk/nrf54l05/cpuapp/s115_softdevice/mcuboot
12+
- bm_nrf54l15dk/nrf54l05/cpuapp/s145_softdevice
13+
- bm_nrf54l15dk/nrf54l05/cpuapp/s145_softdevice/mcuboot
14+
- bm_nrf54l15dk/nrf54l10/cpuapp/s115_softdevice
15+
- bm_nrf54l15dk/nrf54l10/cpuapp/s115_softdevice/mcuboot
16+
- bm_nrf54l15dk/nrf54l10/cpuapp/s145_softdevice
17+
- bm_nrf54l15dk/nrf54l10/cpuapp/s145_softdevice/mcuboot
18+
- bm_nrf54l15dk/nrf54l15/cpuapp/s115_softdevice
19+
- bm_nrf54l15dk/nrf54l15/cpuapp/s115_softdevice/mcuboot
20+
- bm_nrf54l15dk/nrf54l15/cpuapp/s145_softdevice
21+
- bm_nrf54l15dk/nrf54l15/cpuapp/s145_softdevice/mcuboot
22+
- bm_nrf54lm20dk/nrf54lm20a/cpuapp/s115_softdevice
23+
- bm_nrf54lm20dk/nrf54lm20a/cpuapp/s115_softdevice/mcuboot
24+
- bm_nrf54lm20dk/nrf54lm20a/cpuapp/s145_softdevice
25+
- bm_nrf54lm20dk/nrf54lm20a/cpuapp/s145_softdevice/mcuboot
26+
- bm_nrf54ls05dk/nrf54ls05b/cpuapp/s115_softdevice
27+
- bm_nrf54ls05dk/nrf54ls05b/cpuapp/s115_softdevice/mcuboot
28+
- bm_nrf54ls05dk/nrf54ls05b/cpuapp/s145_softdevice
29+
- bm_nrf54ls05dk/nrf54ls05b/cpuapp/s145_softdevice/mcuboot
30+
- bm_nrf54lv10dk/nrf54lv10a/cpuapp/s115_softdevice
31+
- bm_nrf54lv10dk/nrf54lv10a/cpuapp/s115_softdevice/mcuboot
32+
- bm_nrf54lv10dk/nrf54lv10a/cpuapp/s145_softdevice
33+
- bm_nrf54lv10dk/nrf54lv10a/cpuapp/s145_softdevice/mcuboot
34+
tags: ci_build

0 commit comments

Comments
 (0)