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samples: peripherals: spi_mngr: add SPI manager NOR flash sample
Add a non-blocking sample that exercises read, page program, and sector erase on the on-board external NOR flash through the SPI manager library. Buttons trigger the operations and the read result is logged as a hex dump. Wire up BOARD_EXTERNAL_MEMORY_* macros (SPIM instance, SCK/MOSI/MISO/CS and WP#/RST# strap pins) in the affected board-config.h files so the sample picks up the on-board flash automatically. Signed-off-by: Martynas Smilingis <martynas.smilingis@nordicsemi.no>
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‎boards/nordic/bm_nrf54l15dk/include/board-config.h‎

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@@ -63,6 +63,30 @@ extern "C" {
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#define BOARD_CONSOLE_UARTE_PIN_CTS NRF_PIN_PORT_TO_PIN_NUMBER(7, 1)
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#endif
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/* External SPI memory pins. */
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#ifndef BOARD_EXTERNAL_MEMORY_SPIM_INST
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#define BOARD_EXTERNAL_MEMORY_SPIM_INST NRF_SPIM00
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#endif
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#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_SCK
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#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_SCK NRF_PIN_PORT_TO_PIN_NUMBER(1, 2)
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#endif
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#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_MOSI
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#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_MOSI NRF_PIN_PORT_TO_PIN_NUMBER(2, 2)
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#endif
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#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_MISO
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#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_MISO NRF_PIN_PORT_TO_PIN_NUMBER(4, 2)
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#endif
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#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_CSN
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#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_CSN NRF_PIN_PORT_TO_PIN_NUMBER(5, 2)
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#endif
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#ifndef BOARD_EXTERNAL_MEMORY_PIN_WP
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#define BOARD_EXTERNAL_MEMORY_PIN_WP NRF_PIN_PORT_TO_PIN_NUMBER(3, 2)
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#endif
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#ifndef BOARD_EXTERNAL_MEMORY_PIN_RST
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#define BOARD_EXTERNAL_MEMORY_PIN_RST NRF_PIN_PORT_TO_PIN_NUMBER(0, 2)
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#endif
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/* Application UART configuration */
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#ifndef BOARD_APP_UARTE_INST
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#define BOARD_APP_UARTE_INST NRF_UARTE30

‎boards/nordic/bm_nrf54lm20dk/include/board-config.h‎

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#define BOARD_CONSOLE_UARTE_PIN_CTS NRF_PIN_PORT_TO_PIN_NUMBER(19, 1)
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#endif
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/* External SPI memory pins. */
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#ifndef BOARD_EXTERNAL_MEMORY_SPIM_INST
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#define BOARD_EXTERNAL_MEMORY_SPIM_INST NRF_SPIM00
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#endif
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#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_SCK
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#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_SCK NRF_PIN_PORT_TO_PIN_NUMBER(1, 2)
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#endif
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#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_MOSI
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#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_MOSI NRF_PIN_PORT_TO_PIN_NUMBER(2, 2)
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#endif
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#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_MISO
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#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_MISO NRF_PIN_PORT_TO_PIN_NUMBER(4, 2)
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#endif
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#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_CSN
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#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_CSN NRF_PIN_PORT_TO_PIN_NUMBER(5, 2)
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#endif
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#ifndef BOARD_EXTERNAL_MEMORY_PIN_WP
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#define BOARD_EXTERNAL_MEMORY_PIN_WP NRF_PIN_PORT_TO_PIN_NUMBER(3, 2)
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#endif
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#ifndef BOARD_EXTERNAL_MEMORY_PIN_RST
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#define BOARD_EXTERNAL_MEMORY_PIN_RST NRF_PIN_PORT_TO_PIN_NUMBER(0, 2)
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#endif
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/* Application UART configuration */
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#ifndef BOARD_APP_UARTE_INST
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#define BOARD_APP_UARTE_INST NRF_UARTE30

‎doc/nrf-bm/includes/supported_boards_with_external_flash_memory_mcuboot_variants_s115.txt‎

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**S115**:
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.. list-table::
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:header-rows: 1
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* - Hardware platform
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- PCA
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- Board target
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* - `nRF54L15 DK`_
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- PCA10156
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- bm_nrf54l15dk/nrf54l15/cpuapp/s115_softdevice/mcuboot
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* - `nRF54L15 DK`_ (emulating nRF54L10)
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- PCA10156
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- bm_nrf54l15dk/nrf54l10/cpuapp/s115_softdevice/mcuboot
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* - `nRF54L15 DK`_ (emulating nRF54L05)
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- PCA10156
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- bm_nrf54l15dk/nrf54l05/cpuapp/s115_softdevice/mcuboot
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* - `nRF54LM20 DK`_
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- PCA10184
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- bm_nrf54lm20dk/nrf54lm20a/cpuapp/s115_softdevice/mcuboot

‎doc/nrf-bm/includes/supported_boards_with_external_flash_memory_mcuboot_variants_s145.txt‎

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**S145**:
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.. list-table::
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:header-rows: 1
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* - Hardware platform
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- PCA
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- Board target
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* - `nRF54L15 DK`_
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- PCA10156
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- bm_nrf54l15dk/nrf54l15/cpuapp/s145_softdevice/mcuboot
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* - `nRF54L15 DK`_ (emulating nRF54L10)
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- PCA10156
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- bm_nrf54l15dk/nrf54l10/cpuapp/s145_softdevice/mcuboot
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* - `nRF54L15 DK`_ (emulating nRF54L05)
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- PCA10156
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- bm_nrf54l15dk/nrf54l05/cpuapp/s145_softdevice/mcuboot
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* - `nRF54LM20 DK`_
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- PCA10184
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- bm_nrf54lm20dk/nrf54lm20a/cpuapp/s145_softdevice/mcuboot

‎doc/nrf-bm/includes/supported_boards_with_external_flash_memory_non-mcuboot_variants_s115.txt‎

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**S115**:
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.. list-table::
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:header-rows: 1
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* - Hardware platform
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- PCA
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- Board target
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* - `nRF54L15 DK`_
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- PCA10156
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- bm_nrf54l15dk/nrf54l15/cpuapp/s115_softdevice
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* - `nRF54L15 DK`_ (emulating nRF54L10)
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- PCA10156
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- bm_nrf54l15dk/nrf54l10/cpuapp/s115_softdevice
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* - `nRF54L15 DK`_ (emulating nRF54L05)
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- PCA10156
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- bm_nrf54l15dk/nrf54l05/cpuapp/s115_softdevice
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* - `nRF54LM20 DK`_
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- PCA10184
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- bm_nrf54lm20dk/nrf54lm20a/cpuapp/s115_softdevice

‎doc/nrf-bm/includes/supported_boards_with_external_flash_memory_non-mcuboot_variants_s145.txt‎

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**S145**:
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.. list-table::
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:header-rows: 1
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* - Hardware platform
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- PCA
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- Board target
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* - `nRF54L15 DK`_
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- PCA10156
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- bm_nrf54l15dk/nrf54l15/cpuapp/s145_softdevice
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* - `nRF54L15 DK`_ (emulating nRF54L10)
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- PCA10156
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- bm_nrf54l15dk/nrf54l10/cpuapp/s145_softdevice
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* - `nRF54L15 DK`_ (emulating nRF54L05)
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- PCA10156
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- bm_nrf54l15dk/nrf54l05/cpuapp/s145_softdevice
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* - `nRF54LM20 DK`_
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- PCA10184
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- bm_nrf54lm20dk/nrf54lm20a/cpuapp/s145_softdevice

‎doc/nrf-bm/release_notes/release_notes_changelog.rst‎

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Boards
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======
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No changes since the latest nRF Connect SDK Bare Metal release.
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* Added ``BOARD_EXTERNAL_MEMORY_*`` macros to **bm_nrf54l15dk** and **bm_nrf54lm20dk** ``board-config.h`` (SPIM instance, SCK/MOSI/MISO/CS and WP#/RST# strap pins) for on-board SPI external flash. Other BM development kits do not include external flash memory on the board, so their ``board-config.h`` files omit these macros.
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Build system
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============
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Peripheral samples
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------------------
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No changes since the latest nRF Connect SDK Bare Metal release.
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* Added the :ref:`spi_mngr_sample` sample, demonstrating non-blocking read, page program, and sector erase on the on-board external NOR flash using the :ref:`lib_bm_spi_mngr` library.
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DFU samples
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-----------

‎samples/peripherals/spi_mngr/CMakeLists.txt‎

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#
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# Copyright (c) 2026 Nordic Semiconductor ASA
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#
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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#
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cmake_minimum_required(VERSION 3.20.0)
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find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
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project(spi_mngr)
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target_sources(app PRIVATE src/main.c)

‎samples/peripherals/spi_mngr/Kconfig‎

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#
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# Copyright (c) 2026 Nordic Semiconductor ASA
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#
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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#
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menu "SPI Manager sample"
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config SAMPLE_SPI_MNGR_MSG
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string "Message to write to external NOR flash"
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default "Hello World!"
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help
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Payload bytes written to the external NOR flash when a program operation is triggered.
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Truncated to 64 bytes if longer.
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module=SAMPLE_SPI_MNGR
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module-str=SPI manager sample
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source "$(ZEPHYR_BASE)/subsys/logging/Kconfig.template.log_config"
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endmenu # "SPI Manager sample"
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source "Kconfig.zephyr"

‎samples/peripherals/spi_mngr/README.rst‎

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.. _spi_mngr_sample:
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SPI manager external memory
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###########################
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.. contents::
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:local:
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:depth: 2
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The SPI manager sample demonstrates how to use the :ref:`lib_bm_spi_mngr` library with |BMlong| to perform non-blocking read, page program, and sector erase operations on the external flash memory of the development kit.
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Requirements
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************
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Use a development kit with **on-board SPI external flash** and ``BOARD_EXTERNAL_MEMORY_*`` in :file:`board-config.h` (**nRF54L15 DK** and **nRF54LM20 DK** only). The nRF54LV10 and nRF54LS05 DKs have no on-board external flash for this sample and are not listed.
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The following board targets match :file:`sample.yaml`:
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.. tabs::
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.. group-tab:: Simple board variants
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The following board variants do **not** have DFU capabilities:
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.. include:: /includes/supported_boards_with_external_flash_memory_non-mcuboot_variants_s115.txt
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.. include:: /includes/supported_boards_with_external_flash_memory_non-mcuboot_variants_s145.txt
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.. group-tab:: MCUboot board variants
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The following board variants have DFU capabilities:
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.. include:: /includes/supported_boards_with_external_flash_memory_mcuboot_variants_s115.txt
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.. include:: /includes/supported_boards_with_external_flash_memory_mcuboot_variants_s145.txt
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.. important::
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Enable **external storage** in **nRF Connect for Desktop** → **Board Configurator**, then write the configuration to the board. Without that, the on-board flash may not be powered or routed to the SoC, and the sample does not work.
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Overview
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********
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The sample uses the SPI manager library to schedule read, program, and erase operations on the external flash without blocking the CPU. All operations target the same flash address (``FLASH_ADDR`` in :file:`main.c`) and share a single SPI manager instance.
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The flash is the on-board MX25-class NOR device on the development kit. Its SPI and strap pins are defined by the ``BOARD_EXTERNAL_MEMORY_*`` macros in :file:`board-config.h`.
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User interface
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**************
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LED 0:
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Lit when the device is initialized.
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Button 1:
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Erase the flash sector.
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Button 2:
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Read from the flash and log the data as a hex dump.
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Button 3:
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Program the message defined by :kconfig:option:`CONFIG_SAMPLE_SPI_MNGR_MSG` to the flash.
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Configuration
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*************
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Set the message written to flash through the following Kconfig option:
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* :kconfig:option:`CONFIG_SAMPLE_SPI_MNGR_MSG`. String written to the external flash during a program operation. The string is truncated to 64 bytes if longer. The default value is ``"Hello World!"``.
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Building and running
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********************
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This sample can be found under :file:`samples/peripherals/spi_mngr/` in the |BMshort| folder structure.
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For details on how to create, configure, and program a sample, see :ref:`getting_started_with_the_samples`.
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Testing
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=======
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Make sure that you have enabled **external storage** in the Board Configurator (see the note in the Requirements section) before flashing the sample.
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You can then test the sample by performing the following steps:
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1. Compile and program the application.
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#. Open a serial terminal and observe the startup log, which lists the buttons and their operations.
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#. Press **Button 2** to read the on-board flash. The hex dump shows either all ``0xFF`` (erased) or whatever was last written to the address in a previous session.
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#. Press **Button 3** to program the configured message. The log prints ``Programming "Hello World!" @ 0x00100000``.
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#. Press **Button 2** again. The hex dump now starts with the message bytes, confirming that the write succeeded. For the default configuration, this is ``48 65 6c 6c 6f 20 57 6f 72 6c 64 21`` followed by ``0xFF`` padding.
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#. Power-cycle the board and press **Button 2** without programming again. The same message reappears, which confirms that the data is non-volatile and persists in the external flash across resets.
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#. Press **Button 1** to erase the sector. Wait a moment for the chip to finish the self-timed erase.
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#. Power-cycle the board and press **Button 2**. The hex dump shows all ``0xFF`` again, which confirms that the erase removed the data.
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#. Optionally, change :kconfig:option:`CONFIG_SAMPLE_SPI_MNGR_MSG` to a different string, rebuild, and repeat steps 4 to 6 to verify that your custom message is written and persists across reboots.

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