samples: peripherals: spi_mngr: add SPI manager NOR flash sample

PizzaAllTheWay · PizzaAllTheWay · commit a45033ed4ce4 · 2026-06-03T10:51:12.000+02:00
Add a non-blocking sample that exercises read, page program, and
sector erase on the on-board external NOR flash through the SPI
manager library. Buttons trigger the operations and the read result
is logged as a hex dump.

Wire up BOARD_EXTERNAL_MEMORY_* macros (SPIM instance, SCK/MOSI/MISO/CS
and WP#/RST# strap pins) in the affected board-config.h files so the
sample picks up the on-board flash automatically.

Signed-off-by: Martynas Smilingis &lt;martynas.smilingis@nordicsemi.no&gt;
diff --git a/boards/nordic/bm_nrf54l15dk/include/board-config.h b/boards/nordic/bm_nrf54l15dk/include/board-config.h
@@ -63,6 +63,30 @@ extern "C" {
 #define BOARD_CONSOLE_UARTE_PIN_CTS NRF_PIN_PORT_TO_PIN_NUMBER(7, 1)
 #endif
 
+/* External SPI memory pins. */
+#ifndef BOARD_EXTERNAL_MEMORY_SPIM_INST
+#define BOARD_EXTERNAL_MEMORY_SPIM_INST NRF_SPIM00
+#endif
+
+#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_SCK
+#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_SCK NRF_PIN_PORT_TO_PIN_NUMBER(1, 2)
+#endif
+#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_MOSI
+#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_MOSI NRF_PIN_PORT_TO_PIN_NUMBER(2, 2)
+#endif
+#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_MISO
+#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_MISO NRF_PIN_PORT_TO_PIN_NUMBER(4, 2)
+#endif
+#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_CSN
+#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_CSN NRF_PIN_PORT_TO_PIN_NUMBER(5, 2)
+#endif
+#ifndef BOARD_EXTERNAL_MEMORY_PIN_WP
+#define BOARD_EXTERNAL_MEMORY_PIN_WP NRF_PIN_PORT_TO_PIN_NUMBER(3, 2)
+#endif
+#ifndef BOARD_EXTERNAL_MEMORY_PIN_RST
+#define BOARD_EXTERNAL_MEMORY_PIN_RST NRF_PIN_PORT_TO_PIN_NUMBER(0, 2)
+#endif
+
 /* Application UART configuration */
 #ifndef BOARD_APP_UARTE_INST
 #define BOARD_APP_UARTE_INST NRF_UARTE30
diff --git a/boards/nordic/bm_nrf54lm20dk/include/board-config.h b/boards/nordic/bm_nrf54lm20dk/include/board-config.h
@@ -63,6 +63,30 @@ extern "C" {
 #define BOARD_CONSOLE_UARTE_PIN_CTS NRF_PIN_PORT_TO_PIN_NUMBER(19, 1)
 #endif
 
+/* External SPI memory pins. */
+#ifndef BOARD_EXTERNAL_MEMORY_SPIM_INST
+#define BOARD_EXTERNAL_MEMORY_SPIM_INST NRF_SPIM00
+#endif
+
+#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_SCK
+#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_SCK NRF_PIN_PORT_TO_PIN_NUMBER(1, 2)
+#endif
+#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_MOSI
+#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_MOSI NRF_PIN_PORT_TO_PIN_NUMBER(2, 2)
+#endif
+#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_MISO
+#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_MISO NRF_PIN_PORT_TO_PIN_NUMBER(4, 2)
+#endif
+#ifndef BOARD_EXTERNAL_MEMORY_SPIM_PIN_CSN
+#define BOARD_EXTERNAL_MEMORY_SPIM_PIN_CSN NRF_PIN_PORT_TO_PIN_NUMBER(5, 2)
+#endif
+#ifndef BOARD_EXTERNAL_MEMORY_PIN_WP
+#define BOARD_EXTERNAL_MEMORY_PIN_WP NRF_PIN_PORT_TO_PIN_NUMBER(3, 2)
+#endif
+#ifndef BOARD_EXTERNAL_MEMORY_PIN_RST
+#define BOARD_EXTERNAL_MEMORY_PIN_RST NRF_PIN_PORT_TO_PIN_NUMBER(0, 2)
+#endif
+
 /* Application UART configuration */
 #ifndef BOARD_APP_UARTE_INST
 #define BOARD_APP_UARTE_INST NRF_UARTE30
diff --git a/doc/nrf-bm/includes/supported_boards_with_external_flash_memory_mcuboot_variants_s115.txt b/doc/nrf-bm/includes/supported_boards_with_external_flash_memory_mcuboot_variants_s115.txt
@@ -0,0 +1,20 @@
+**S115**:
+
+      .. list-table::
+         :header-rows: 1
+
+         * - Hardware platform
+           - PCA
+           - Board target
+         * - `nRF54L15 DK`_
+           - PCA10156
+           - bm_nrf54l15dk/nrf54l15/cpuapp/s115_softdevice/mcuboot
+         * - `nRF54L15 DK`_ (emulating nRF54L10)
+           - PCA10156
+           - bm_nrf54l15dk/nrf54l10/cpuapp/s115_softdevice/mcuboot
+         * - `nRF54L15 DK`_ (emulating nRF54L05)
+           - PCA10156
+           - bm_nrf54l15dk/nrf54l05/cpuapp/s115_softdevice/mcuboot
+         * - `nRF54LM20 DK`_
+           - PCA10184
+           - bm_nrf54lm20dk/nrf54lm20a/cpuapp/s115_softdevice/mcuboot
diff --git a/doc/nrf-bm/includes/supported_boards_with_external_flash_memory_mcuboot_variants_s145.txt b/doc/nrf-bm/includes/supported_boards_with_external_flash_memory_mcuboot_variants_s145.txt
@@ -0,0 +1,20 @@
+**S145**:
+
+      .. list-table::
+         :header-rows: 1
+
+         * - Hardware platform
+           - PCA
+           - Board target
+         * - `nRF54L15 DK`_
+           - PCA10156
+           - bm_nrf54l15dk/nrf54l15/cpuapp/s145_softdevice/mcuboot
+         * - `nRF54L15 DK`_ (emulating nRF54L10)
+           - PCA10156
+           - bm_nrf54l15dk/nrf54l10/cpuapp/s145_softdevice/mcuboot
+         * - `nRF54L15 DK`_ (emulating nRF54L05)
+           - PCA10156
+           - bm_nrf54l15dk/nrf54l05/cpuapp/s145_softdevice/mcuboot
+         * - `nRF54LM20 DK`_
+           - PCA10184
+           - bm_nrf54lm20dk/nrf54lm20a/cpuapp/s145_softdevice/mcuboot
diff --git a/doc/nrf-bm/includes/supported_boards_with_external_flash_memory_non-mcuboot_variants_s115.txt b/doc/nrf-bm/includes/supported_boards_with_external_flash_memory_non-mcuboot_variants_s115.txt
@@ -0,0 +1,20 @@
+**S115**:
+
+      .. list-table::
+         :header-rows: 1
+
+         * - Hardware platform
+           - PCA
+           - Board target
+         * - `nRF54L15 DK`_
+           - PCA10156
+           - bm_nrf54l15dk/nrf54l15/cpuapp/s115_softdevice
+         * - `nRF54L15 DK`_ (emulating nRF54L10)
+           - PCA10156
+           - bm_nrf54l15dk/nrf54l10/cpuapp/s115_softdevice
+         * - `nRF54L15 DK`_ (emulating nRF54L05)
+           - PCA10156
+           - bm_nrf54l15dk/nrf54l05/cpuapp/s115_softdevice
+         * - `nRF54LM20 DK`_
+           - PCA10184
+           - bm_nrf54lm20dk/nrf54lm20a/cpuapp/s115_softdevice
diff --git a/doc/nrf-bm/includes/supported_boards_with_external_flash_memory_non-mcuboot_variants_s145.txt b/doc/nrf-bm/includes/supported_boards_with_external_flash_memory_non-mcuboot_variants_s145.txt
@@ -0,0 +1,20 @@
+**S145**:
+
+      .. list-table::
+         :header-rows: 1
+
+         * - Hardware platform
+           - PCA
+           - Board target
+         * - `nRF54L15 DK`_
+           - PCA10156
+           - bm_nrf54l15dk/nrf54l15/cpuapp/s145_softdevice
+         * - `nRF54L15 DK`_ (emulating nRF54L10)
+           - PCA10156
+           - bm_nrf54l15dk/nrf54l10/cpuapp/s145_softdevice
+         * - `nRF54L15 DK`_ (emulating nRF54L05)
+           - PCA10156
+           - bm_nrf54l15dk/nrf54l05/cpuapp/s145_softdevice
+         * - `nRF54LM20 DK`_
+           - PCA10184
+           - bm_nrf54lm20dk/nrf54lm20a/cpuapp/s145_softdevice
diff --git a/doc/nrf-bm/libraries/bm_spi_mngr.rst b/doc/nrf-bm/libraries/bm_spi_mngr.rst
@@ -98,6 +98,11 @@ Busy state
 
 Use the :c:func:`bm_spi_mngr_is_idle` function to check whether all scheduled work has finished.
 
+Sample
+******
+
+The usage of this library is demonstrated in the :ref:`spi_mngr_sample` sample.
+
 Dependencies
 ************
 
diff --git a/doc/nrf-bm/links.txt b/doc/nrf-bm/links.txt
@@ -91,6 +91,7 @@
 .. _`How to flash an application`: https://docs.nordicsemi.com/bundle/nrf-connect-vscode/page/get_started/quick_debug.html#how-to-flash-an-application
 .. _`How to connect to the terminal`: https://docs.nordicsemi.com/bundle/nrf-connect-vscode/page/get_started/quick_debug.html#how-to-connect-to-the-terminal
 .. _`nRF Connect for Desktop`: https://www.nordicsemi.com/Software-and-Tools/Development-Tools/nRF-Connect-for-desktop
+.. _Board Configurator: https://docs.nordicsemi.com/bundle/nrf-connect-board-configurator/page/index.html
 .. _`additional requirements`: https://docs.nordicsemi.com/bundle/nrf-connect-desktop/page/download_cfd.html
 .. _`nRF Connect Device Manager`: https://www.nordicsemi.com/Products/Development-tools/nRF-Connect-Device-Manager
 .. _`nRF Toolbox`: https://www.nordicsemi.com/Software-and-Tools/Development-Tools/nRF-Toolbox
diff --git a/doc/nrf-bm/release_notes/release_notes_changelog.rst b/doc/nrf-bm/release_notes/release_notes_changelog.rst
@@ -33,7 +33,7 @@ No changes since the latest nRF Connect SDK Bare Metal release.
 Boards
 ======
 
-No changes since the latest nRF Connect SDK Bare Metal release.
+* Added ``BOARD_EXTERNAL_MEMORY_*`` macros to **bm_nrf54l15dk** and **bm_nrf54lm20dk** ``board-config.h`` (SPIM instance, SCK/MOSI/MISO/CS and WP#/RST# strap pins) for on-board SPI external flash. Other BM development kits do not include external flash memory on the board, so their ``board-config.h`` files omit these macros.
 
 Build system
 ============
@@ -120,7 +120,7 @@ No changes since the latest nRF Connect SDK Bare Metal release.
 Peripheral samples
 ------------------
 
-No changes since the latest nRF Connect SDK Bare Metal release.
+* Added the :ref:`spi_mngr_sample` sample, demonstrating non-blocking read, page program, and sector erase on the on-board external NOR flash using the :ref:`lib_bm_spi_mngr` library.
 
 DFU samples
 -----------
diff --git a/samples/peripherals/spi_mngr/CMakeLists.txt b/samples/peripherals/spi_mngr/CMakeLists.txt
@@ -0,0 +1,12 @@
+#
+# Copyright (c) 2026 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+#
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(spi_mngr)
+
+target_sources(app PRIVATE src/main.c)
diff --git a/samples/peripherals/spi_mngr/Kconfig b/samples/peripherals/spi_mngr/Kconfig
@@ -0,0 +1,22 @@
+#
+# Copyright (c) 2026 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+#
+
+menu "SPI Manager sample"
+
+config SAMPLE_SPI_MNGR_MSG
+	string "Message to write to external NOR flash"
+	default "Hello World!"
+	help
+	  Payload bytes written to the external NOR flash when a program operation is triggered.
+	  Truncated to 64 bytes if longer.
+
+module=SAMPLE_SPI_MNGR
+module-str=SPI manager sample
+source "$(ZEPHYR_BASE)/subsys/logging/Kconfig.template.log_config"
+
+endmenu # "SPI Manager sample"
+
+source "Kconfig.zephyr"
diff --git a/samples/peripherals/spi_mngr/README.rst b/samples/peripherals/spi_mngr/README.rst
@@ -0,0 +1,96 @@
+.. _spi_mngr_sample:
+
+SPI manager external memory
+###########################
+
+.. contents::
+   :local:
+   :depth: 2
+
+The SPI manager sample demonstrates how to use the :ref:`lib_bm_spi_mngr` library with |BMlong| to perform non-blocking read, page program, and sector erase operations on the external flash memory of the development kit.
+
+Requirements
+************
+
+This sample is designed to run on a development kit with **on-board SPI external flash**, which is configured through the ``BOARD_EXTERNAL_MEMORY_*`` macros in :file:`board-config.h`.
+Currently, only the `nRF54L15 DK`_ and `nRF54LM20 DK`_ include on-board external flash and are therefore the supported targets for this sample.
+
+The following board targets match :file:`sample.yaml`:
+
+.. tabs::
+
+   .. group-tab:: Simple board variants
+
+      The following board variants do **not** have DFU capabilities:
+
+      .. include:: /includes/supported_boards_with_external_flash_memory_non-mcuboot_variants_s115.txt
+
+      .. include:: /includes/supported_boards_with_external_flash_memory_non-mcuboot_variants_s145.txt
+
+   .. group-tab:: MCUboot board variants
+
+      The following board variants have DFU capabilities:
+
+      .. include:: /includes/supported_boards_with_external_flash_memory_mcuboot_variants_s115.txt
+
+      .. include:: /includes/supported_boards_with_external_flash_memory_mcuboot_variants_s145.txt
+
+.. note::
+   The `nRF54LV10 DK`_ and `nRF54LS05 DK`_ do **not** have on-board external flash memory and are therefore out of scope for this sample.
+   However, the :ref:`lib_bm_spi_mngr` library itself is fully supported on these devkits.
+   You can still use the SPI manager feature on these boards by connecting your own external SPI slave device (for example, an external NOR flash) to the SPI pins of the SoC and adapting the sample configuration accordingly (pin assignments in :file:`board-config.h`, command set, and timing parameters to match your device).
+
+.. important::
+   Before flashing the sample, you must enable **External memory** using the `Board Configurator`_ app in `nRF Connect for Desktop`_, and then write the configuration to the board.
+   Without this step, the on-board flash is not powered or routed to the SoC, and the sample will not work.
+
+Overview
+********
+
+The sample uses the SPI manager library to schedule read, program, and erase operations on the external flash without blocking the CPU.
+All operations target the same flash address (``FLASH_ADDR`` in :file:`main.c`) and share a single SPI manager instance.
+
+The flash is the on-board MX25-class NOR device on the development kit.
+Its SPI and strap pins are defined by the ``BOARD_EXTERNAL_MEMORY_*`` macros in :file:`board-config.h`.
+
+User interface
+**************
+
+LED 0:
+  Lit when the device is initialized.
+
+Button 1:
+  Erase external memory.
+
+Button 2:
+  Read external memory.
+
+Button 3:
+  Program external memory.
+
+Building and running
+********************
+
+This sample can be found under :file:`samples/peripherals/spi_mngr/` in the |BMshort| folder structure.
+
+For details on how to create, configure, and program a sample, see :ref:`getting_started_with_the_samples`.
+
+Testing
+=======
+
+You can test this sample by performing the following steps:
+
+1. Compile and program the application.
+#. Observe that the ``SPI manager sample initialized`` message is printed, followed by the list of available buttons and their operations.
+#. Press **Button 2** to read the on-board flash.
+   The hex dump shows either all ``0xFF`` (erased) or the data last written to the address.
+#. Press **Button 3** to program the configured message (set with :kconfig:option:`CONFIG_SAMPLE_SPI_MNGR_MSG`, default ``Hello World!``).
+   The log prints ``Programming "Hello World!" @ 0x00100000``.
+#. Press **Button 2** again.
+   The hex dump now starts with the message bytes, confirming the write succeeded.
+   For the default configuration, this is ``48 65 6c 6c 6f 20 57 6f 72 6c 64 21`` (ASCII for ``Hello World!``), followed by ``0xFF`` padding.
+#. Power-cycle the board and press **Button 2**.
+   The same message reappears, confirming the data persists across power cycles.
+#. Press **Button 1** to erase the sector and wait for the self-timed erase to finish.
+#. Power-cycle the board again and press **Button 2**.
+   The hex dump shows all ``0xFF``, confirming the erase succeeded.
diff --git a/samples/peripherals/spi_mngr/prj.conf b/samples/peripherals/spi_mngr/prj.conf
@@ -0,0 +1,19 @@
+# Logging
+CONFIG_LOG=y
+CONFIG_LOG_BACKEND_BM_UARTE=y
+
+# Enabling SoftDevice is not strictly needed, though we are building with SoftDevice boards.
+CONFIG_SOFTDEVICE=y
+
+# Buttons, LEDs ans timer
+CONFIG_BM_BUTTONS=y
+CONFIG_BM_GPIOTE=y
+CONFIG_BM_TIMER=y
+
+# HFCLK and related clock services for SoC peripherals.
+CONFIG_CLOCK_CONTROL=y
+
+# SPIM hardware driver, required by bm_spi_mngr for SPI master transfers.
+CONFIG_NRFX_SPIM=y
+# Queued SPI transactions on top of nrfx SPIM.
+CONFIG_BM_SPI_MNGR=y
diff --git a/samples/peripherals/spi_mngr/sample.yaml b/samples/peripherals/spi_mngr/sample.yaml
@@ -0,0 +1,26 @@
+sample:
+  name: SPI Manager Sample
+tests:
+  sample.spi_mngr:
+    sysbuild: true
+    build_only: true
+    integration_platforms:
+      - bm_nrf54l15dk/nrf54l15/cpuapp/s115_softdevice
+    platform_allow:
+      - bm_nrf54l15dk/nrf54l05/cpuapp/s115_softdevice
+      - bm_nrf54l15dk/nrf54l05/cpuapp/s115_softdevice/mcuboot
+      - bm_nrf54l15dk/nrf54l05/cpuapp/s145_softdevice
+      - bm_nrf54l15dk/nrf54l05/cpuapp/s145_softdevice/mcuboot
+      - bm_nrf54l15dk/nrf54l10/cpuapp/s115_softdevice
+      - bm_nrf54l15dk/nrf54l10/cpuapp/s115_softdevice/mcuboot
+      - bm_nrf54l15dk/nrf54l10/cpuapp/s145_softdevice
+      - bm_nrf54l15dk/nrf54l10/cpuapp/s145_softdevice/mcuboot
+      - bm_nrf54l15dk/nrf54l15/cpuapp/s115_softdevice
+      - bm_nrf54l15dk/nrf54l15/cpuapp/s115_softdevice/mcuboot
+      - bm_nrf54l15dk/nrf54l15/cpuapp/s145_softdevice
+      - bm_nrf54l15dk/nrf54l15/cpuapp/s145_softdevice/mcuboot
+      - bm_nrf54lm20dk/nrf54lm20a/cpuapp/s115_softdevice
+      - bm_nrf54lm20dk/nrf54lm20a/cpuapp/s115_softdevice/mcuboot
+      - bm_nrf54lm20dk/nrf54lm20a/cpuapp/s145_softdevice
+      - bm_nrf54lm20dk/nrf54lm20a/cpuapp/s145_softdevice/mcuboot
+    tags: ci_build
diff --git a/samples/peripherals/spi_mngr/src/main.c b/samples/peripherals/spi_mngr/src/main.c
